Lines Matching +full:0 +full:x160
17 { HI3670_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
18 { HI3670_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
19 { HI3670_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 134400000, },
20 { HI3670_CLK_PPLL0, "clk_ppll0", NULL, 0, 1660000000, },
21 { HI3670_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
22 { HI3670_CLK_PPLL2, "clk_ppll2", NULL, 0, 1920000000, },
23 { HI3670_CLK_PPLL3, "clk_ppll3", NULL, 0, 1200000000, },
24 { HI3670_CLK_PPLL4, "clk_ppll4", NULL, 0, 900000000, },
25 { HI3670_CLK_PPLL6, "clk_ppll6", NULL, 0, 393216000, },
26 { HI3670_CLK_PPLL7, "clk_ppll7", NULL, 0, 1008000000, },
27 { HI3670_CLK_PPLL_PCIE, "clk_ppll_pcie", NULL, 0, 100000000, },
28 { HI3670_CLK_PCIEPLL_REV, "clk_pciepll_rev", NULL, 0, 100000000, },
29 { HI3670_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, },
30 { HI3670_PCLK, "pclk", NULL, 0, 20000000, },
31 { HI3670_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, },
32 { HI3670_CLK_UART6, "clk_uart6", NULL, 0, 19200000, },
33 { HI3670_OSC32K, "osc32k", NULL, 0, 32764, },
34 { HI3670_OSC19M, "osc19m", NULL, 0, 19200000, },
35 { HI3670_CLK_480M, "clk_480m", NULL, 0, 480000000, },
36 { HI3670_CLK_INVALID, "clk_invalid", NULL, 0, 10000000, },
42 1, 7, 0, },
44 1, 6, 0, },
46 1, 6, 0, },
48 1, 6, 0, },
50 1, 4, 0, },
52 1, 5, 0, },
54 1, 1, 0, },
56 1, 1, 0, },
58 1, 60, 0, },
60 1, 1, 0, },
62 1, 1, 0, },
64 1, 1, 0, },
66 1, 1, 0, },
68 1, 1, 0, },
70 1, 1, 0, },
72 1, 1, 0, },
74 1, 10, 0, },
76 1, 6, 0, },
81 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
83 CLK_SET_RATE_PARENT, 0x0, 3, 0, },
85 CLK_SET_RATE_PARENT, 0x0, 27, 0, },
87 CLK_SET_RATE_PARENT, 0x460, 16, 0, },
89 CLK_SET_RATE_PARENT, 0x460, 18, 0, },
91 CLK_SET_RATE_PARENT, 0x460, 20, 0, },
93 CLK_SET_RATE_PARENT, 0x410, 27, 0, },
95 CLK_SET_RATE_PARENT, 0x410, 28, 0, },
97 CLK_SET_RATE_PARENT, 0x410, 26, 0, },
99 CLK_SET_RATE_PARENT, 0x410, 30, 0, },
101 CLK_SET_RATE_PARENT, 0x410, 29, 0, },
103 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
105 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
107 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
109 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
111 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
113 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
115 CLK_SET_RATE_PARENT, 0x10, 6, 0, },
117 CLK_SET_RATE_PARENT, 0x10, 7, 0, },
119 CLK_SET_RATE_PARENT, 0x10, 8, 0, },
121 CLK_SET_RATE_PARENT, 0x10, 9, 0, },
123 CLK_SET_RATE_PARENT, 0x10, 10, 0, },
125 CLK_SET_RATE_PARENT, 0x10, 11, 0, },
127 CLK_SET_RATE_PARENT, 0x10, 12, 0, },
129 CLK_SET_RATE_PARENT, 0x10, 13, 0, },
131 CLK_SET_RATE_PARENT, 0x10, 14, 0, },
133 CLK_SET_RATE_PARENT, 0x10, 15, 0, },
135 CLK_SET_RATE_PARENT, 0x10, 16, 0, },
137 CLK_SET_RATE_PARENT, 0x10, 17, 0, },
139 CLK_SET_RATE_PARENT, 0x10, 20, 0, },
141 CLK_SET_RATE_PARENT, 0x10, 21, 0, },
143 CLK_SET_RATE_PARENT, 0x50, 28, 0, },
145 CLK_SET_RATE_PARENT, 0x50, 29, 0, },
147 CLK_SET_RATE_PARENT, 0x0, 25, 0, },
149 CLK_SET_RATE_PARENT, 0x40, 1, 0, },
151 CLK_SET_RATE_PARENT, 0x0, 21, 0, },
153 CLK_SET_RATE_PARENT, 0x420, 7, 0, },
155 CLK_SET_RATE_PARENT, 0x420, 9, 0, },
157 CLK_SET_RATE_PARENT, 0x30, 12, 0, },
159 CLK_SET_RATE_PARENT, 0x40, 13, 0, },
161 CLK_SET_RATE_PARENT, 0x420, 21, 0, },
163 CLK_SET_RATE_PARENT, 0x30, 1, 0, },
165 CLK_SET_RATE_PARENT, 0x0, 5, 0, },
167 CLK_SET_RATE_PARENT, 0x22C, 28, 0, },
169 CLK_SET_RATE_PARENT, 0x50, 14, 0, },
171 CLK_SET_RATE_PARENT, 0x40, 17, 0, },
173 CLK_SET_RATE_PARENT, 0x0, 30, 0, },
175 CLK_SET_RATE_PARENT, 0x40, 19, 0, },
177 CLK_SET_RATE_PARENT, 0x050, 9, 0, },
179 CLK_SET_RATE_PARENT, 0x050, 13, 0, },
181 CLK_SET_RATE_PARENT, 0x480, 10, 0, },
183 CLK_SET_RATE_PARENT, 0x480, 9, 0, },
185 CLK_SET_RATE_PARENT, 0x480, 15, 0, },
187 CLK_SET_RATE_PARENT, 0x050, 15, 0, },
189 CLK_SET_RATE_PARENT, 0x050, 12, 0, },
191 CLK_SET_RATE_PARENT, 0x050, 11, 0, },
193 CLK_SET_RATE_PARENT, 0x20, 11, 0, },
195 CLK_SET_RATE_PARENT, 0x20, 14, 0, },
197 CLK_SET_RATE_PARENT, 0x20, 11, 0, },
199 CLK_SET_RATE_PARENT, 0x20, 14, 0, },
201 CLK_SET_RATE_PARENT, 0x20, 12, 0, },
203 CLK_SET_RATE_PARENT, 0x20, 15, 0, },
205 CLK_SET_RATE_PARENT, 0x20, 12, 0, },
207 CLK_SET_RATE_PARENT, 0x20, 15, 0, },
209 CLK_SET_RATE_PARENT, 0x20, 10, 0, },
211 CLK_SET_RATE_PARENT, 0x20, 7, 0, },
213 CLK_SET_RATE_PARENT, 0x20, 27, 0, },
215 CLK_SET_RATE_PARENT, 0x10, 31, 0, },
217 CLK_SET_RATE_PARENT, 0x20, 7, 0, },
219 CLK_SET_RATE_PARENT, 0x20, 27, 0, },
221 CLK_SET_RATE_PARENT, 0x10, 31, 0, },
223 CLK_SET_RATE_PARENT, 0x20, 9, 0, },
225 CLK_SET_RATE_PARENT, 0x40, 4, 0, },
227 CLK_SET_RATE_PARENT, 0x20, 9, 0, },
229 CLK_SET_RATE_PARENT, 0x40, 4, 0, },
231 CLK_SET_RATE_PARENT, 0x40, 0, 0, },
233 CLK_SET_RATE_PARENT, 0x410, 19, 0, },
235 CLK_SET_RATE_PARENT, 0x420, 8, 0, },
237 CLK_SET_RATE_PARENT, 0x420, 5, 0, },
239 CLK_SET_RATE_PARENT, 0x050, 4, 0, },
241 CLK_SET_RATE_PARENT, 0x470, 14, 0, },
243 CLK_SET_RATE_PARENT, 0x470, 12, 0, },
245 CLK_SET_RATE_PARENT, 0x470, 13, 0, },
247 CLK_SET_RATE_PARENT, 0x470, 15, 0, },
249 CLK_SET_RATE_PARENT, 0x0, 26, 0, },
251 CLK_SET_RATE_PARENT, 0x20, 31, 0, },
253 CLK_SET_RATE_PARENT, 0x30, 24, 0, },
255 CLK_SET_RATE_PARENT, 0x30, 25, 0, },
257 CLK_SET_RATE_PARENT, 0x20, 0, 0, },
259 CLK_SET_RATE_PARENT, 0x30, 8, 0, },
261 CLK_SET_RATE_PARENT, 0x30, 9, 0, },
263 CLK_SET_RATE_PARENT, 0x30, 19, 0, },
265 CLK_SET_RATE_PARENT, 0x40, 20, 0, },
267 CLK_SET_RATE_PARENT, 0x00, 13, 0, },
269 CLK_SET_RATE_PARENT, 0, 1, 0, },
271 CLK_SET_RATE_PARENT, 0, 1, 0, },
273 CLK_SET_RATE_PARENT, 0x50, 16, 0, },
275 CLK_SET_RATE_PARENT, 0x50, 17, 0, },
277 CLK_SET_RATE_PARENT, 0x50, 18, 0, },
279 CLK_SET_RATE_PARENT, 0x030, 20, 0, },
281 CLK_SET_RATE_PARENT, 0x030, 21, 0, },
283 CLK_SET_RATE_PARENT, 0x030, 22, 0, },
285 CLK_SET_RATE_PARENT, 0x030, 28, 0, },
287 CLK_SET_RATE_PARENT, 0x030, 29, 0, },
289 CLK_SET_RATE_PARENT, 0x030, 30, 0, },
291 CLK_SET_RATE_PARENT, 0x030, 31, 0, },
293 CLK_SET_RATE_PARENT, 0x40, 6, 0, },
298 CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, },
300 CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, },
302 CLK_SET_RATE_PARENT, 0xf8, 13, CLK_GATE_HIWORD_MASK, },
304 CLK_SET_RATE_PARENT, 0x0F0, 8, CLK_GATE_HIWORD_MASK, },
306 CLK_SET_RATE_PARENT, 0xF4, 3, CLK_GATE_HIWORD_MASK, },
308 CLK_SET_RATE_PARENT, 0xF4, 5, CLK_GATE_HIWORD_MASK, },
310 CLK_SET_RATE_PARENT, 0xF4, 8, CLK_GATE_HIWORD_MASK, },
312 CLK_SET_RATE_PARENT, 0xF4, 6, CLK_GATE_HIWORD_MASK, },
314 CLK_SET_RATE_PARENT, 0x0F4, 7, CLK_GATE_HIWORD_MASK, },
316 CLK_SET_RATE_PARENT, 0xF8, 10, CLK_GATE_HIWORD_MASK, },
318 CLK_SET_RATE_PARENT, 0xF4, 11, CLK_GATE_HIWORD_MASK, },
320 CLK_SET_RATE_PARENT, 0xF4, 10, CLK_GATE_HIWORD_MASK, },
322 CLK_SET_RATE_PARENT, 0xF4, 9, CLK_GATE_HIWORD_MASK, },
324 CLK_SET_RATE_PARENT, 0xF4, 13, CLK_GATE_HIWORD_MASK, },
326 CLK_SET_RATE_PARENT, 0xfc, 15, CLK_GATE_HIWORD_MASK, },
328 CLK_SET_RATE_PARENT, 0xF4, 4, CLK_GATE_HIWORD_MASK, },
330 CLK_SET_RATE_PARENT, 0xF4, 14, CLK_GATE_HIWORD_MASK, },
332 CLK_SET_RATE_PARENT, 0xF4, 1, CLK_GATE_HIWORD_MASK, },
334 CLK_SET_RATE_PARENT, 0xF8, 5, CLK_GATE_HIWORD_MASK, },
336 CLK_SET_RATE_PARENT, 0xF0, 10, CLK_GATE_HIWORD_MASK, },
338 CLK_SET_RATE_PARENT, 0xF0, 11, CLK_GATE_HIWORD_MASK, },
340 CLK_SET_RATE_PARENT, 0xF8, 15, CLK_GATE_HIWORD_MASK, },
342 CLK_SET_RATE_PARENT, 0xF0, 13, CLK_GATE_HIWORD_MASK, },
344 CLK_SET_RATE_PARENT, 0xF0, 9, CLK_GATE_HIWORD_MASK, },
346 CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, },
348 CLK_SET_RATE_PARENT, 0x0F0, 12, CLK_GATE_HIWORD_MASK, },
350 CLK_SET_RATE_PARENT, 0xf0, 14, CLK_GATE_HIWORD_MASK, },
352 CLK_SET_RATE_PARENT, 0x404, 3, CLK_GATE_HIWORD_MASK, },
420 0xAC, 0, 1, CLK_MUX_HIWORD_MASK, },
423 0x0C8, 0, 4, CLK_MUX_HIWORD_MASK, },
426 0x0B8, 6, 1, CLK_MUX_HIWORD_MASK, },
429 0x0B8, 4, 2, CLK_MUX_HIWORD_MASK, },
432 0x0C0, 6, 1, CLK_MUX_HIWORD_MASK, },
435 0x0C0, 4, 2, CLK_MUX_HIWORD_MASK, },
438 0x0D4, 9, 1, CLK_MUX_HIWORD_MASK, },
441 0x100, 0, 1, CLK_MUX_HIWORD_MASK, },
444 0xAC, 4, 1, CLK_MUX_HIWORD_MASK, },
447 0xAC, 3, 1, CLK_MUX_HIWORD_MASK, },
450 0xAC, 2, 1, CLK_MUX_HIWORD_MASK, },
453 0xAC, 13, 1, CLK_MUX_HIWORD_MASK, },
456 0xAC, 8, 1, CLK_MUX_HIWORD_MASK, },
459 0xb4, 5, 1, CLK_MUX_HIWORD_MASK, },
462 0x100, 6, 1, CLK_MUX_HIWORD_MASK, },
465 0xC8, 8, 4, CLK_MUX_HIWORD_MASK, },
468 0xC8, 4, 4, CLK_MUX_HIWORD_MASK, },
471 0x108, 3, 1, CLK_MUX_HIWORD_MASK, },
474 0x10C, 13, 1, CLK_MUX_HIWORD_MASK, },
477 0x10C, 10, 1, CLK_MUX_HIWORD_MASK, },
480 0x0C4, 8, 1, CLK_MUX_HIWORD_MASK, },
483 0xc8, 12, 4, CLK_MUX_HIWORD_MASK, },
488 CLK_SET_RATE_PARENT, 0xEC, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
490 CLK_SET_RATE_PARENT, 0x0EC, 2, 1, CLK_DIVIDER_HIWORD_MASK, },
492 CLK_SET_RATE_PARENT, 0x0EC, 3, 1, CLK_DIVIDER_HIWORD_MASK, },
494 CLK_SET_RATE_PARENT, 0xb4, 6, 4, CLK_DIVIDER_HIWORD_MASK, },
496 CLK_SET_RATE_PARENT, 0x0BC, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
498 CLK_SET_RATE_PARENT, 0xB8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
500 CLK_SET_RATE_PARENT, 0xC0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
502 CLK_SET_RATE_PARENT, 0xB0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
504 CLK_SET_RATE_PARENT, 0xB0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
506 CLK_SET_RATE_PARENT, 0xB0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
508 CLK_SET_RATE_PARENT, 0xE8, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
510 CLK_SET_RATE_PARENT, 0xC4, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
512 CLK_SET_RATE_PARENT, 0xb4, 0, 5, CLK_DIVIDER_HIWORD_MASK, },
514 CLK_SET_RATE_PARENT, 0x108, 6, 4, CLK_DIVIDER_HIWORD_MASK, },
516 CLK_SET_RATE_PARENT, 0xD4, 0, 5, CLK_DIVIDER_HIWORD_MASK, },
518 CLK_SET_RATE_PARENT, 0xD4, 10, 5, CLK_DIVIDER_HIWORD_MASK, },
520 CLK_SET_RATE_PARENT, 0xD8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
522 CLK_SET_RATE_PARENT, 0xe0, 4, 6, CLK_DIVIDER_HIWORD_MASK, },
524 CLK_SET_RATE_PARENT, 0xe0, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
526 CLK_SET_RATE_PARENT, 0xBC, 11, 4, CLK_DIVIDER_HIWORD_MASK, },
528 CLK_SET_RATE_PARENT, 0xC4, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
530 CLK_SET_RATE_PARENT, 0xC0, 8, 6, CLK_DIVIDER_HIWORD_MASK, },
532 CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
534 CLK_SET_RATE_PARENT, 0x10C, 14, 2, CLK_DIVIDER_HIWORD_MASK, },
536 CLK_SET_RATE_PARENT, 0x10C, 11, 2, CLK_DIVIDER_HIWORD_MASK, },
538 CLK_SET_RATE_PARENT, 0xE4, 9, 6, CLK_DIVIDER_HIWORD_MASK, },
544 CLK_SET_RATE_PARENT, (0x037 << 2), 0, 0, },
550 CLK_SET_RATE_PARENT, 0x10, 0, CLK_GATE_HIWORD_MASK, },
552 CLK_SET_RATE_PARENT, 0x10, 1, CLK_GATE_HIWORD_MASK, },
558 CLK_SET_RATE_PARENT, 0x190, 26, 0, },
560 CLK_SET_RATE_PARENT, 0x190, 15, 0, },
562 CLK_SET_RATE_PARENT, 0x1b0, 6, 0, },
564 CLK_SET_RATE_PARENT, 0x1B0, 9, 0, },
566 CLK_SET_RATE_PARENT, 0x1B0, 8, 0, },
568 CLK_SET_RATE_PARENT, 0x1B0, 10, 0, },
570 CLK_SET_RATE_PARENT, 0x1B0, 10, 0, },
572 CLK_SET_RATE_PARENT, 0x1B0, 14, 0, },
574 CLK_SET_RATE_PARENT, 0x1b0, 12, 0, },
576 CLK_SET_RATE_PARENT, 0x160, 11, 0, },
578 CLK_SET_RATE_PARENT, 0x160, 12, 0, },
580 CLK_SET_RATE_PARENT, 0x160, 13, 0, },
582 CLK_SET_RATE_PARENT, 0x160, 14, 0, },
584 CLK_SET_RATE_PARENT, 0x160, 21, 0, },
586 CLK_SET_RATE_PARENT, 0x160, 22, 0, },
588 CLK_SET_RATE_PARENT, 0x160, 25, 0, },
590 CLK_SET_RATE_PARENT, 0x160, 16, 0, },
592 CLK_SET_RATE_PARENT, 0x160, 17, 0, },
594 CLK_SET_RATE_PARENT, 0x160, 19, 0, },
596 CLK_SET_RATE_PARENT, 0x160, 20, 0, },
599 CLK_SET_RATE_PARENT, 0x170, 6, 0, },
601 CLK_SET_RATE_PARENT, 0x170, 4, 0, },
603 CLK_SET_RATE_PARENT, 0x160, 27, 0, },
606 CLK_SET_RATE_PARENT, 0x1B0, 7, 0, },
611 CLK_SET_RATE_PARENT, 0x270, 6, CLK_GATE_HIWORD_MASK, },
614 CLK_SET_RATE_PARENT, 0x268, 3, CLK_GATE_HIWORD_MASK, },
616 CLK_SET_RATE_PARENT, 0x258, 0, CLK_GATE_HIWORD_MASK, },
636 0x274, 8, 1, CLK_MUX_HIWORD_MASK, },
639 0x254, 12, 2, CLK_MUX_HIWORD_MASK, },
642 0x254, 14, 2, CLK_MUX_HIWORD_MASK, },
645 CLK_SET_RATE_PARENT, 0x268, 8, 1, CLK_MUX_HIWORD_MASK, },
648 0x268, 9, 2, CLK_MUX_HIWORD_MASK, },
653 CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
655 CLK_SET_RATE_PARENT, 0x274, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
657 CLK_SET_RATE_PARENT, 0x270, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
659 CLK_SET_RATE_PARENT, 0x254, 6, 3, CLK_DIVIDER_HIWORD_MASK, },
661 CLK_SET_RATE_PARENT, 0x254, 9, 3, CLK_DIVIDER_HIWORD_MASK, },
663 CLK_SET_RATE_PARENT, 0x268, 0, 3, CLK_DIVIDER_HIWORD_MASK, },
665 CLK_SET_RATE_PARENT, 0x250, 0, 3, CLK_DIVIDER_HIWORD_MASK, },
670 { HI3670_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_gate_iomcu", 1, 4, 0, },
671 { HI3670_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_gate_iomcu", 1, 4, 0, },
672 { HI3670_CLK_GATE_I2C2, "clk_gate_i2c2", "clk_i2c2_gate_iomcu", 1, 4, 0, },
673 { HI3670_CLK_GATE_SPI0, "clk_gate_spi0", "clk_spi0_gate_iomcu", 1, 1, 0, },
674 { HI3670_CLK_GATE_SPI2, "clk_gate_spi2", "clk_spi2_gate_iomcu", 1, 1, 0, },
675 { HI3670_CLK_GATE_UART3, "clk_gate_uart3", "clk_uart3_gate_iomcu", 1, 16, 0, },
680 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
682 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
684 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
686 CLK_SET_RATE_PARENT, 0x10, 10, 0, },
688 CLK_SET_RATE_PARENT, 0x10, 30, 0, },
690 CLK_SET_RATE_PARENT, 0x10, 11, 0, },
692 CLK_SET_RATE_PARENT, 0x90, 0, 0, },
698 CLK_SET_RATE_PARENT, 0x10, 21, 0, },
700 CLK_SET_RATE_PARENT, 0x10, 22, 0, },
702 CLK_SET_RATE_PARENT, 0x20, 5, 0, },
704 CLK_SET_RATE_PARENT, 0x10, 18, 0, },
706 CLK_SET_RATE_PARENT, 0x10, 17, 0, },
708 CLK_SET_RATE_PARENT, 0x00, 14, 0, },
710 CLK_SET_RATE_PARENT, 0x00, 19, 0, },
712 CLK_SET_RATE_PARENT, 0x00, 18, 0, },
714 CLK_SET_RATE_PARENT, 0x00, 15, 0, },
716 CLK_SET_RATE_PARENT, 0x00, 16, 0, },
718 CLK_SET_RATE_PARENT, 0x00, 17, 0, },
720 CLK_SET_RATE_PARENT, 0x00, 29, 0, },
722 CLK_SET_RATE_PARENT, 0x20, 3, 0, },
724 CLK_SET_RATE_PARENT, 0x20, 4, 0, },
726 CLK_SET_RATE_PARENT, 0x20, 0, 0, },
728 CLK_SET_RATE_PARENT, 0x20, 1, 0, },
730 CLK_SET_RATE_PARENT, 0x010, 1, 0, },
735 CLK_SET_RATE_PARENT, 0x84, 3, CLK_GATE_HIWORD_MASK, },
737 CLK_SET_RATE_PARENT, 0x84, 7, CLK_GATE_HIWORD_MASK, },
739 CLK_SET_RATE_PARENT, 0x84, 9, CLK_GATE_HIWORD_MASK, },
741 CLK_SET_RATE_PARENT, 0x84, 8, CLK_GATE_HIWORD_MASK, },
743 CLK_SET_RATE_PARENT, 0x84, 14, CLK_GATE_HIWORD_MASK, },
745 CLK_SET_RATE_PARENT, 0x84, 15, CLK_GATE_HIWORD_MASK, },
785 0x74, 6, 4, CLK_MUX_HIWORD_MASK, },
788 0x68, 6, 4, CLK_MUX_HIWORD_MASK, },
791 0x60, 6, 4, CLK_MUX_HIWORD_MASK, },
794 0x64, 6, 4, CLK_MUX_HIWORD_MASK, },
797 0x88, 0, 4, CLK_MUX_HIWORD_MASK, },
802 CLK_SET_RATE_PARENT, 0x74, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
804 CLK_SET_RATE_PARENT, 0x68, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
806 CLK_SET_RATE_PARENT, 0x60, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
808 CLK_SET_RATE_PARENT, 0x64, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
810 CLK_SET_RATE_PARENT, 0x7C, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
812 CLK_SET_RATE_PARENT, 0x78, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
818 CLK_SET_RATE_PARENT, 0x00, 8, 0, },
820 CLK_SET_RATE_PARENT, 0x00, 5, 0, },
822 CLK_SET_RATE_PARENT, 0x00, 2, 0, },
1001 return 0; in hi3670_clk_probe()