Lines Matching +full:0 +full:x160
14 { HI3660_CLKIN_SYS, "clkin_sys", NULL, 0, 19200000, },
15 { HI3660_CLKIN_REF, "clkin_ref", NULL, 0, 32764, },
16 { HI3660_CLK_FLL_SRC, "clk_fll_src", NULL, 0, 128000000, },
17 { HI3660_CLK_PPLL0, "clk_ppll0", NULL, 0, 1600000000, },
18 { HI3660_CLK_PPLL1, "clk_ppll1", NULL, 0, 1866000000, },
19 { HI3660_CLK_PPLL2, "clk_ppll2", NULL, 0, 2880000000UL, },
20 { HI3660_CLK_PPLL3, "clk_ppll3", NULL, 0, 1290000000, },
21 { HI3660_CLK_SCPLL, "clk_scpll", NULL, 0, 245760000, },
22 { HI3660_PCLK, "pclk", NULL, 0, 20000000, },
23 { HI3660_CLK_UART0_DBG, "clk_uart0_dbg", NULL, 0, 19200000, },
24 { HI3660_CLK_UART6, "clk_uart6", NULL, 0, 19200000, },
25 { HI3660_OSC32K, "osc32k", NULL, 0, 32764, },
26 { HI3660_OSC19M, "osc19m", NULL, 0, 19200000, },
27 { HI3660_CLK_480M, "clk_480m", NULL, 0, 480000000, },
28 { HI3660_CLK_INV, "clk_inv", NULL, 0, 10000000, },
33 { HI3660_FACTOR_UART3, "clk_factor_uart3", "iomcu_peri0", 1, 16, 0, },
34 { HI3660_CLK_FACTOR_MMC, "clk_factor_mmc", "clkin_sys", 1, 6, 0, },
35 { HI3660_CLK_GATE_I2C0, "clk_gate_i2c0", "clk_i2c0_iomcu", 1, 4, 0, },
36 { HI3660_CLK_GATE_I2C1, "clk_gate_i2c1", "clk_i2c1_iomcu", 1, 4, 0, },
37 { HI3660_CLK_GATE_I2C2, "clk_gate_i2c2", "clk_i2c2_iomcu", 1, 4, 0, },
38 { HI3660_CLK_GATE_I2C6, "clk_gate_i2c6", "clk_i2c6_iomcu", 1, 4, 0, },
39 { HI3660_CLK_DIV_SYSBUS, "clk_div_sysbus", "clk_mux_sysbus", 1, 7, 0, },
40 { HI3660_CLK_DIV_320M, "clk_div_320m", "clk_320m_pll_gt", 1, 5, 0, },
41 { HI3660_CLK_DIV_A53, "clk_div_a53hpm", "clk_a53hpm_andgt", 1, 6, 0, },
42 { HI3660_CLK_GATE_SPI0, "clk_gate_spi0", "clk_ppll0", 1, 8, 0, },
43 { HI3660_CLK_GATE_SPI2, "clk_gate_spi2", "clk_ppll0", 1, 8, 0, },
44 { HI3660_PCIEPHY_REF, "clk_pciephy_ref", "clk_div_pciephy", 1, 1, 0, },
45 { HI3660_CLK_ABB_USB, "clk_abb_usb", "clk_gate_usb_tcxo_en", 1, 1, 0 },
46 { HI3660_VENC_VOLT_HOLD, "venc_volt_hold", "peri_volt_hold", 1, 1, 0, },
48 1, 10, 0, },
53 CLK_SET_RATE_PARENT, 0x0, 0, 0, },
55 CLK_SET_RATE_PARENT, 0x0, 21, 0, },
57 CLK_SET_RATE_PARENT, 0x0, 30, 0, },
59 CLK_SET_RATE_PARENT, 0x0, 31, 0, },
61 CLK_SET_RATE_PARENT, 0x10, 0, 0, },
63 CLK_SET_RATE_PARENT, 0x10, 1, 0, },
65 CLK_SET_RATE_PARENT, 0x10, 2, 0, },
67 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
69 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
71 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
73 CLK_SET_RATE_PARENT, 0x10, 6, 0, },
75 CLK_SET_RATE_PARENT, 0x10, 7, 0, },
77 CLK_SET_RATE_PARENT, 0x10, 8, 0, },
79 CLK_SET_RATE_PARENT, 0x10, 9, 0, },
81 CLK_SET_RATE_PARENT, 0x10, 10, 0, },
83 CLK_SET_RATE_PARENT, 0x10, 11, 0, },
85 CLK_SET_RATE_PARENT, 0x10, 12, 0, },
87 CLK_SET_RATE_PARENT, 0x10, 13, 0, },
89 CLK_SET_RATE_PARENT, 0x10, 14, 0, },
91 CLK_SET_RATE_PARENT, 0x10, 15, 0, },
93 CLK_SET_RATE_PARENT, 0x10, 16, 0, },
95 CLK_SET_RATE_PARENT, 0x10, 17, 0, },
97 CLK_SET_RATE_PARENT, 0x10, 18, 0, },
99 CLK_SET_RATE_PARENT, 0x10, 19, 0, },
101 CLK_SET_RATE_PARENT, 0x10, 20, 0, },
103 CLK_SET_RATE_PARENT, 0x10, 21, 0, },
105 CLK_SET_RATE_PARENT, 0x10, 30, 0, },
107 CLK_SET_RATE_PARENT, 0x10, 31, 0, },
109 CLK_SET_RATE_PARENT, 0x20, 7, 0, },
111 CLK_SET_RATE_PARENT, 0x20, 9, 0, },
113 CLK_SET_RATE_PARENT, 0x20, 11, 0, },
115 CLK_SET_RATE_PARENT, 0x20, 12, 0, },
117 CLK_SET_RATE_PARENT, 0x20, 14, 0, },
119 CLK_SET_RATE_PARENT, 0x20, 15, 0, },
121 CLK_SET_RATE_PARENT, 0x20, 27, 0, },
123 CLK_SET_RATE_PARENT, 0x30, 1, 0, },
125 CLK_SET_RATE_PARENT, 0x30, 10, 0, },
127 CLK_SET_RATE_PARENT, 0x30, 11, 0, },
129 CLK_SET_RATE_PARENT, 0x30, 12, 0, },
131 CLK_SET_RATE_PARENT, 0x30, 13, 0, },
133 CLK_SET_RATE_PARENT, 0x30, 14, 0, },
135 CLK_SET_RATE_PARENT, 0x30, 15, 0, },
137 CLK_SET_RATE_PARENT, 0x30, 16, 0, },
139 CLK_SET_RATE_PARENT, 0x30, 17, 0, },
141 CLK_SET_RATE_PARENT, 0x30, 28, 0, },
143 CLK_SET_RATE_PARENT, 0x30, 29, 0, },
145 CLK_SET_RATE_PARENT, 0x30, 30, 0, },
147 CLK_SET_RATE_PARENT, 0x30, 31, 0, },
149 CLK_SET_RATE_PARENT, 0x40, 1, 0, },
151 CLK_SET_RATE_PARENT, 0x40, 4, 0, },
153 CLK_SET_RATE_PARENT, 0x40, 17, 0, },
155 CLK_SET_RATE_PARENT, 0x40, 19, 0, },
157 "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 16, 0, },
159 "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 17, 0, },
161 "clk_isp_snclk_mux", CLK_SET_RATE_PARENT, 0x50, 18, 0, },
167 CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, 0x50, 21, 0, },
169 CLK_SET_RATE_PARENT, 0x50, 28, 0, },
171 CLK_SET_RATE_PARENT, 0x50, 29, 0, },
173 CLK_SET_RATE_PARENT, 0x420, 5, 0, },
175 CLK_SET_RATE_PARENT, 0x420, 7, 0, },
177 CLK_SET_RATE_PARENT, 0x420, 8, 0, },
179 CLK_SET_RATE_PARENT, 0x420, 9, 0, },
184 CLK_SET_RATE_PARENT, 0xf0, 6, CLK_GATE_HIWORD_MASK, },
186 CLK_SET_RATE_PARENT, 0xf0, 7, CLK_GATE_HIWORD_MASK, },
188 CLK_SET_RATE_PARENT, 0xf0, 8, CLK_GATE_HIWORD_MASK, },
190 CLK_SET_RATE_PARENT, 0xf0, 15, CLK_GATE_HIWORD_MASK, },
192 CLK_SET_RATE_PARENT, 0xf4, 0, CLK_GATE_HIWORD_MASK, },
194 CLK_SET_RATE_PARENT, 0xf4, 1, CLK_GATE_HIWORD_MASK, },
196 CLK_SET_RATE_PARENT, 0xf4, 2, CLK_GATE_HIWORD_MASK, },
198 CLK_SET_RATE_PARENT, 0xf4, 3, CLK_GATE_HIWORD_MASK, },
200 CLK_SET_RATE_PARENT, 0xf4, 7, CLK_GATE_HIWORD_MASK, },
202 CLK_SET_RATE_PARENT, 0xf4, 8, CLK_GATE_HIWORD_MASK, },
204 CLK_SET_RATE_PARENT, 0xf4, 9, CLK_GATE_HIWORD_MASK, },
206 CLK_SET_RATE_PARENT, 0xf4, 10, CLK_GATE_HIWORD_MASK, },
208 CLK_SET_RATE_PARENT, 0xf4, 11, CLK_GATE_HIWORD_MASK, },
210 CLK_SET_RATE_PARENT, 0xf4, 13, CLK_GATE_HIWORD_MASK, },
212 CLK_SET_RATE_PARENT, 0xf8, 1, CLK_GATE_HIWORD_MASK, },
214 CLK_SET_RATE_PARENT, 0xf8, 3, CLK_GATE_HIWORD_MASK, },
216 CLK_SET_RATE_PARENT, 0xf8, 10, 0, },
218 CLK_SET_RATE_PARENT, 0x108, 2, CLK_GATE_HIWORD_MASK, },
220 CLK_SET_RATE_PARENT, 0x404, 1, CLK_GATE_HIWORD_MASK, },
222 CLK_SET_RATE_PARENT, 0x404, 5, CLK_GATE_HIWORD_MASK, },
224 "clk_div_ufsphy_cfg", CLK_SET_RATE_PARENT, 0x420, 12, 0, },
226 "clk_gate_ufs_tcxo_en", CLK_SET_RATE_PARENT, 0x420, 14, 0, },
270 ARRAY_SIZE(clk_mux_sysbus_p), CLK_SET_RATE_PARENT, 0xac, 0, 1,
273 ARRAY_SIZE(clk_mux_uart0_p), CLK_SET_RATE_PARENT, 0xac, 2, 1,
276 ARRAY_SIZE(clk_mux_uart1_p), CLK_SET_RATE_PARENT, 0xac, 3, 1,
279 ARRAY_SIZE(clk_mux_uarth_p), CLK_SET_RATE_PARENT, 0xac, 4, 1,
282 ARRAY_SIZE(clk_mux_spi_p), CLK_SET_RATE_PARENT, 0xac, 8, 1,
285 ARRAY_SIZE(clk_mux_i2c_p), CLK_SET_RATE_PARENT, 0xac, 13, 1,
288 ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xb4, 0, 1,
291 ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 8, 4,
294 ARRAY_SIZE(clk_mux_ldi0_p), CLK_SET_RATE_PARENT, 0xb4, 12, 4,
297 ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xb8, 4, 2,
300 ARRAY_SIZE(clk_mux_sd_sys_p), CLK_SET_RATE_PARENT, 0xb8, 6, 1,
303 ARRAY_SIZE(clk_mux_edc0_p), CLK_SET_RATE_PARENT, 0xbc, 6, 4,
306 ARRAY_SIZE(clk_mux_sdio_sys_p), CLK_SET_RATE_PARENT, 0xc0, 6, 1,
309 ARRAY_SIZE(clk_mux_pll_p), CLK_SET_RATE_PARENT, 0xc0, 4, 2,
312 ARRAY_SIZE(clk_mux_venc_p), CLK_SET_RATE_PARENT, 0xc8, 11, 2,
315 ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xcc, 5, 2,
318 ARRAY_SIZE(clk_mux_pll0123_p), CLK_SET_RATE_PARENT, 0xd0, 12, 2,
321 ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0xd4, 9, 1,
324 ARRAY_SIZE(clk_mux_pll02p), CLK_SET_RATE_PARENT, 0x100, 0, 1,
327 ARRAY_SIZE(clk_mux_isp_snclk_p), CLK_SET_RATE_PARENT, 0x108, 3, 1,
330 ARRAY_SIZE(clk_mux_ioperi_p), CLK_SET_RATE_PARENT, 0x108, 10, 1,
336 CLK_SET_RATE_PARENT, 0xb0, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
338 CLK_SET_RATE_PARENT, 0xb0, 8, 4, CLK_DIVIDER_HIWORD_MASK, },
340 CLK_SET_RATE_PARENT, 0xb0, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
342 CLK_SET_RATE_PARENT, 0xb4, 3, 4, CLK_DIVIDER_HIWORD_MASK, },
344 CLK_SET_RATE_PARENT, 0xb8, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
346 CLK_SET_RATE_PARENT, 0xbc, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
348 CLK_SET_RATE_PARENT, 0xbc, 10, 6, CLK_DIVIDER_HIWORD_MASK, },
350 CLK_SET_RATE_PARENT, 0xc0, 0, 4, CLK_DIVIDER_HIWORD_MASK, },
352 CLK_SET_RATE_PARENT, 0xc0, 8, 6, CLK_DIVIDER_HIWORD_MASK, },
354 CLK_SET_RATE_PARENT, 0xc4, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
356 CLK_SET_RATE_PARENT, 0xc8, 6, 5, CLK_DIVIDER_HIWORD_MASK, },
358 CLK_SET_RATE_PARENT, 0xcc, 0, 5, CLK_DIVIDER_HIWORD_MASK, },
360 CLK_SET_RATE_PARENT, 0xd0, 7, 5, CLK_DIVIDER_HIWORD_MASK, },
362 CLK_SET_RATE_PARENT, 0xe8, 4, 4, CLK_DIVIDER_HIWORD_MASK, },
364 CLK_SET_RATE_PARENT, 0xe8, 9, 2, CLK_DIVIDER_HIWORD_MASK, },
366 CLK_SET_RATE_PARENT, 0xec, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
368 CLK_SET_RATE_PARENT, 0xec, 2, 1, CLK_DIVIDER_HIWORD_MASK, },
370 CLK_SET_RATE_PARENT, 0xec, 3, 1, CLK_DIVIDER_HIWORD_MASK, },
372 CLK_SET_RATE_PARENT, 0xec, 14, 1, CLK_DIVIDER_HIWORD_MASK, },
374 CLK_SET_RATE_PARENT, 0x100, 7, 4, CLK_DIVIDER_HIWORD_MASK, },
376 CLK_SET_RATE_PARENT, 0x108, 0, 2, CLK_DIVIDER_HIWORD_MASK, },
378 CLK_SET_RATE_PARENT, 0x108, 11, 4, CLK_DIVIDER_HIWORD_MASK, },
385 CLK_SET_RATE_PARENT, (0x10a << 2), 3, 0, },
391 "clk_gate_abb_192", CLK_SET_RATE_PARENT, 0x10, 0,
394 CLK_SET_RATE_PARENT, 0x10, 1, CLK_GATE_HIWORD_MASK, },
400 CLK_SET_RATE_PARENT, 0x160, 11, 0, },
402 CLK_SET_RATE_PARENT, 0x160, 12, 0, },
404 CLK_SET_RATE_PARENT, 0x160, 13, 0, },
406 CLK_SET_RATE_PARENT, 0x160, 14, 0, },
408 CLK_SET_RATE_PARENT, 0x160, 21, 0, },
410 CLK_SET_RATE_PARENT, 0x160, 22, 0, },
412 CLK_SET_RATE_PARENT, 0x160, 25, 0, },
414 CLK_SET_RATE_PARENT, 0x170, 23, 0, },
416 CLK_SET_RATE_PARENT, 0x170, 24, 0, },
421 CLK_SET_RATE_PARENT, 0x258, 7, CLK_GATE_HIWORD_MASK, },
423 CLK_SET_RATE_PARENT, 0x260, 11, CLK_DIVIDER_HIWORD_MASK, },
425 CLK_SET_RATE_PARENT, 0x260, 12, CLK_DIVIDER_HIWORD_MASK, },
427 CLK_SET_RATE_PARENT, 0x260, 13, CLK_DIVIDER_HIWORD_MASK, },
429 CLK_SET_RATE_PARENT, 0x268, 11, CLK_DIVIDER_HIWORD_MASK, },
440 ARRAY_SIZE(aclk_mux_mmbuf_p), CLK_SET_RATE_PARENT, 0x250, 12, 1,
443 ARRAY_SIZE(clk_sw_mmbuf_p), CLK_SET_RATE_PARENT, 0x258, 8, 2,
449 CLK_SET_RATE_PARENT, 0x254, 0, 6, CLK_DIVIDER_HIWORD_MASK, },
451 CLK_SET_RATE_PARENT, 0x258, 10, 2, CLK_DIVIDER_HIWORD_MASK, },
453 CLK_SET_RATE_PARENT, 0x258, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
455 CLK_SET_RATE_PARENT, 0x268, 12, 4, CLK_DIVIDER_HIWORD_MASK, },
461 CLK_SET_RATE_PARENT, 0x10, 3, 0, },
463 CLK_SET_RATE_PARENT, 0x10, 4, 0, },
465 CLK_SET_RATE_PARENT, 0x10, 5, 0, },
467 CLK_SET_RATE_PARENT, 0x10, 27, 0, },
469 CLK_SET_RATE_PARENT, 0x90, 0, 0, },
550 for (i = 0; i < nr; i++) in hi3660_clk_crgctrl_early_init()
589 for (i = 0; i < clk_crgctrl_data->clk_data.clk_num; i++) { in hi3660_clk_crgctrl_init()
622 return 0; in hi3660_clk_probe()