Lines Matching refs:pll_val
551 u32 pll_val; in vtwm_pll_set_rate() local
561 pll_val = VT8500_BITS_TO_VAL(mul, div1); in vtwm_pll_set_rate()
566 pll_val = WM8650_BITS_TO_VAL(mul, div1, div2); in vtwm_pll_set_rate()
571 pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2); in vtwm_pll_set_rate()
576 pll_val = WM8850_BITS_TO_VAL(mul, div1, div2); in vtwm_pll_set_rate()
589 writel(pll_val, pll->reg); in vtwm_pll_set_rate()
640 u32 pll_val = readl(pll->reg); in vtwm_pll_recalc_rate() local
645 pll_freq = parent_rate * VT8500_PLL_MUL(pll_val); in vtwm_pll_recalc_rate()
646 pll_freq /= VT8500_PLL_DIV(pll_val); in vtwm_pll_recalc_rate()
649 pll_freq = parent_rate * WM8650_PLL_MUL(pll_val); in vtwm_pll_recalc_rate()
650 pll_freq /= WM8650_PLL_DIV(pll_val); in vtwm_pll_recalc_rate()
653 pll_freq = parent_rate * WM8750_PLL_MUL(pll_val); in vtwm_pll_recalc_rate()
654 pll_freq /= WM8750_PLL_DIV(pll_val); in vtwm_pll_recalc_rate()
657 pll_freq = parent_rate * WM8850_PLL_MUL(pll_val); in vtwm_pll_recalc_rate()
658 pll_freq /= WM8850_PLL_DIV(pll_val); in vtwm_pll_recalc_rate()