Lines Matching +full:5 +full:p49v5923

3  * Driver for IDT Versaclock 5
95 #define VC5_CLK_OUTPUT_CFG0_CFG_SHIFT	5
123 #define VC5_GLOBAL_REGISTER_GLOBAL_RESET	BIT(5)
133 #define VC5_MAX_CLK_OUT_NUM	5
441 	u8 fb[5];  in vc5_pll_recalc_rate()
443 	regmap_bulk_read(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);  in vc5_pll_recalc_rate()
485 	u8 fb[5];  in vc5_pll_set_rate()
493 	return regmap_bulk_write(vc5->regmap, VC5_FEEDBACK_INT_DIV, fb, 5);  in vc5_pll_set_rate()
829 	 * After getting feedback from Renesas, the .5pF steps were the  in vc5_map_cap_value()
837 	 * The Programmer's guide shows XTAL[5:0] but in reality,  in vc5_map_cap_value()
1260 	.clk_out_cnt = 5,
1276 	.clk_out_cnt = 5,
1284 	.clk_out_cnt = 5,
1292 	.clk_out_cnt = 5,
1300 	.clk_out_cnt = 5,
1308 	.clk_out_cnt = 5,
1314 	{ "5p49v5923", .driver_data = (kernel_ulong_t)&idt_5p49v5923_info },
1315 	{ "5p49v5925", .driver_data = (kernel_ulong_t)&idt_5p49v5925_info },
1316 	{ "5p49v5933", .driver_data = (kernel_ulong_t)&idt_5p49v5933_info },
1317 	{ "5p49v5935", .driver_data = (kernel_ulong_t)&idt_5p49v5935_info },
1318 	{ "5p49v60", .driver_data = (kernel_ulong_t)&idt_5p49v60_info },
1319 	{ "5p49v6901", .driver_data = (kernel_ulong_t)&idt_5p49v6901_info },
1320 	{ "5p49v6965", .driver_data = (kernel_ulong_t)&idt_5p49v6965_info },
1321 	{ "5p49v6975", .driver_data = (kernel_ulong_t)&idt_5p49v6975_info },
1327 	{ .compatible = "idt,5p49v5923", .data = &idt_5p49v5923_info },
1328 	{ .compatible = "idt,5p49v5925", .data = &idt_5p49v5925_info },
1329 	{ .compatible = "idt,5p49v5933", .data = &idt_5p49v5933_info },
1330 	{ .compatible = "idt,5p49v5935", .data = &idt_5p49v5935_info },
1331 	{ .compatible = "idt,5p49v60", .data = &idt_5p49v60_info },
1332 	{ .compatible = "idt,5p49v6901", .data = &idt_5p49v6901_info },
1333 	{ .compatible = "idt,5p49v6965", .data = &idt_5p49v6965_info },
1334 	{ .compatible = "idt,5p49v6975", .data = &idt_5p49v6975_info },
1354 MODULE_DESCRIPTION("IDT VersaClock 5 driver");