Lines Matching refs:bitmsk
140 u8 bitmsk; member
221 return !!(src & pfd_mux->bitmsk); in vc3_pfd_mux_get_parent()
229 return regmap_update_bits(vc3->regmap, pfd_mux->offs, pfd_mux->bitmsk, in vc3_pfd_mux_set_parent()
230 index ? pfd_mux->bitmsk : 0); in vc3_pfd_mux_set_parent()
450 return !!(src & div_mux->bitmsk); in vc3_div_mux_get_parent()
458 return regmap_update_bits(vc3->regmap, div_mux->offs, div_mux->bitmsk, in vc3_div_mux_set_parent()
459 index ? div_mux->bitmsk : 0); in vc3_div_mux_set_parent()
562 return !!(val & clk_mux->bitmsk); in vc3_clk_mux_get_parent()
570 return regmap_update_bits(vc3->regmap, clk_mux->offs, clk_mux->bitmsk, in vc3_clk_mux_set_parent()
571 index ? clk_mux->bitmsk : 0); in vc3_clk_mux_set_parent()
598 .bitmsk = BIT(VC3_PLL_OP_CTRL_PLL2_REFIN_SEL)
611 .bitmsk = BIT(VC3_GENERAL_CTR_PLL3_REFIN_SEL)
753 .bitmsk = VC3_GENERAL_CTR_DIV1_SRC_SEL
766 .bitmsk = VC3_PLL3_CHARGE_PUMP_CTRL_OUTDIV3_SRC_SEL
779 .bitmsk = VC3_OUTPUT_CTR_DIV4_SRC_SEL
888 .bitmsk = VC3_SE1_DIV4_CTRL_SE1_CLK_SEL
904 .bitmsk = VC3_SE2_CTRL_REG0_SE2_CLK_SEL
920 .bitmsk = VC3_SE3_DIFF1_CTRL_REG_SE3_CLK_SEL
936 .bitmsk = VC3_DIFF1_CTRL_REG_DIFF1_CLK_SEL
952 .bitmsk = VC3_DIFF2_CTRL_REG_DIFF2_CLK_SEL