Lines Matching +full:stm32f469 +full:- +full:qspi
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Inspired by clk-asm9260.c .
9 #include <linux/clk-provider.h>
26 #include <dt-bindings/clock/stm32fx-clock.h>
52 #define NONE -1
177 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
258 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
333 { STM32F4_RCC_AHB3ENR, 1, "qspi", "ahb_div",
383 [STM32F4_PLL_SSC_DOWN_SPREAD] = "down-spread",
384 [STM32F4_PLL_SSC_CENTER_SPREAD] = "center-spread",
423 * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
440 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
452 if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
492 return ERR_PTR(-ENOMEM);
494 am->bit_idx = bit_idx;
495 am->hw.init = &init;
503 clk = clk_register(dev, &am->hw);
574 { "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 },
575 { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 },
585 { CLK_I2SQ_PDIV, PLL_VCO_I2S, "plli2s-q-div", "plli2s-q",
588 { CLK_SAIQ_PDIV, PLL_VCO_SAI, "pllsai-q-div", "pllsai-q",
591 { NO_IDX, PLL_VCO_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
617 { PLL_I2S, 192, { NULL, "plli2s-q", "plli2s-r" } },
618 { PLL_SAI, 49, { NULL, "pllsai-q", "pllsai-r" } },
622 { PLL, 50, { "pll", "pll-q", "pll-r" } },
623 { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
624 { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
647 bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx));
649 } while (bit_status && --timeout);
667 val = readl(base + pll->offset);
682 if (n < pll->n_start)
683 n = pll->n_start;
695 struct stm32f4_pll_ssc *ssc = &pll->ssc_conf;
703 modeper = DIV_ROUND_CLOSEST(parent_rate, 4 * ssc->mod_freq);
704 incstep = DIV_ROUND_CLOSEST(((1 << 15) - 1) * ssc->mod_depth * ndiv,
710 if (ssc->mod_type)
733 val = readl(base + pll->offset) & ~STM32F4_RCC_PLLCFGR_N_MASK;
736 writel(val, base + pll->offset);
738 if (pll->ssc_enable)
783 pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);
786 stm32f4_pll_disable(pll_div->hw_pll);
791 stm32f4_pll_enable(pll_div->hw_pll);
816 return ERR_PTR(-ENOMEM);
825 pll_div->div.reg = reg;
826 pll_div->div.shift = shift;
827 pll_div->div.width = width;
828 pll_div->div.flags = clk_divider_flags;
829 pll_div->div.lock = lock;
830 pll_div->div.table = table;
831 pll_div->div.hw.init = &init;
833 pll_div->hw_pll = pll_hw;
836 hw = &pll_div->div.hw;
859 return -ENODEV;
864 pll->ssc_enable = true;
865 memcpy(&pll->ssc_conf, conf, sizeof(pll->ssc_conf));
872 val = readl(base + pll->offset);
875 pr_debug("%s: pll: %s, parent: %s, parent-rate: %lu, n: %lu\n",
894 return -EINVAL;
896 ret = of_property_read_u32(np, "st,ssc-modfreq-hz", &conf->mod_freq);
900 ret = of_property_read_u32(np, "st,ssc-moddepth-permyriad",
901 &conf->mod_depth);
903 pr_err("%pOF: missing st,ssc-moddepth-permyriad\n", np);
908 "st,ssc-modmethod",
912 pr_err("%pOF: failed to get st,ssc-modmethod\n", np);
916 conf->mod_type = ret;
919 np, conf->mod_freq, conf->mod_depth, s, conf->mod_type);
938 return ERR_PTR(-ENOMEM);
940 vco = &vco_data[data->pll_num];
942 init.name = vco->vco_name;
948 pll->gate.lock = lock;
949 pll->gate.reg = base + STM32F4_RCC_CR;
950 pll->gate.bit_idx = vco->bit_idx;
951 pll->gate.hw.init = &init;
953 pll->offset = vco->offset;
954 pll->n_start = data->n_start;
955 pll->bit_rdy_idx = vco->bit_rdy_idx;
956 pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;
958 reg = base + pll->offset;
960 pll_hw = &pll->gate.hw;
968 if (data->div_name[i])
969 clk_register_pll_div(data->div_name[i],
970 vco->vco_name,
992 return -EINVAL;
1002 return -EINVAL;
1008 return stm32fx_end_primary_clk - 1 + hweight64(table[0]) +
1016 int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);
1019 return ERR_PTR(-EINVAL);
1069 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx));
1073 } while (bit_status && --timeout);
1108 return ERR_PTR(-ENOMEM);
1116 rgate->bit_rdy_idx = bit_rdy_idx;
1118 rgate->gate.lock = lock;
1119 rgate->gate.reg = reg;
1120 rgate->gate.bit_idx = bit_idx;
1121 rgate->gate.hw.init = &init;
1123 hw = &rgate->gate.hw;
1203 hw = ERR_PTR(-EINVAL);
1210 hw = ERR_PTR(-EINVAL);
1214 gate->reg = reg;
1215 gate->bit_idx = bit_idx;
1216 gate->flags = 0;
1217 gate->lock = lock;
1219 mux->reg = reg;
1220 mux->shift = shift;
1221 mux->mask = 3;
1222 mux->flags = 0;
1225 &mux->hw, &cclk_mux_ops,
1227 &gate->hw, &cclk_gate_ops,
1256 "no-clock", "lse", "lsi", "hse-rtc"
1259 static const char *pll_src = "pll-src";
1263 static const char *dsi_parent[2] = { NULL, "pll-r" };
1265 static const char *lcd_parent[1] = { "pllsai-r-div" };
1267 static const char *i2s_parents[2] = { "plli2s-r", NULL };
1269 static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
1270 "no-clock" };
1272 static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
1278 static const char *spdif_parent[1] = { "plli2s-p" };
1285 static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" };
1315 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1327 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1333 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1342 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1354 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1360 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1387 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1423 CLK_HDMI_CEC, "hdmi-cec",
1430 CLK_SPDIF, "spdif-rx",
1533 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1575 CLK_HDMI_CEC, "hdmi-cec",
1582 CLK_SPDIF, "spdif-rx",
1744 .compatible = "st,stm32f42xx-rcc",
1748 .compatible = "st,stm32f469-rcc",
1752 .compatible = "st,stm32f746-rcc",
1756 .compatible = "st,stm32f769-rcc",
1777 hw = ERR_PTR(-EINVAL);
1781 gate->reg = base + offset_gate;
1782 gate->bit_idx = bit_idx;
1783 gate->flags = 0;
1784 gate->lock = lock;
1785 gate_hw = &gate->hw;
1792 hw = ERR_PTR(-EINVAL);
1796 mux->reg = base + offset_mux;
1797 mux->shift = shift;
1798 mux->mask = mask;
1799 mux->flags = 0;
1800 mux_hw = &mux->hw;
1805 hw = ERR_PTR(-EINVAL);
1850 data = match->data;
1852 stm32fx_end_primary_clk = data->end_primary;
1854 clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk,
1859 stm32f4_gate_map = data->gates_map;
1870 if (of_device_is_compatible(np, "st,stm32f769-rcc")) {
1891 pll_vco_hw = stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],
1895 &data->pll_data[1], &stm32f4_clk_lock);
1898 &data->pll_data[2], &stm32f4_clk_lock);
1906 hw = clk_register_pll_div(post_div->name,
1907 post_div->parent,
1908 post_div->flag,
1909 base + post_div->offset,
1910 post_div->shift,
1911 post_div->width,
1912 post_div->flag_div,
1913 post_div->div_table,
1914 clks[post_div->pll_idx],
1917 if (post_div->idx != NO_IDX)
1918 clks[post_div->idx] = hw;
1948 for (n = 0; n < data->gates_num; n++) {
1953 gd = &data->gates_data[n];
1954 secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
1955 gd->bit_idx;
1962 NULL, gd->name, gd->parent_name, gd->flags,
1963 base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
1967 np, gd->name);
1972 clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
1980 clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
1988 clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
1993 pr_err("Unable to register hse-rtc clock\n");
2005 for (n = 0; n < data->aux_clk_num; n++) {
2009 aux_clk = &data->aux_clk[n];
2011 hw = stm32_register_aux_clk(aux_clk->name,
2012 aux_clk->parent_names, aux_clk->num_parents,
2013 aux_clk->offset_mux, aux_clk->shift,
2014 aux_clk->mask, aux_clk->offset_gate,
2015 aux_clk->bit_idx, aux_clk->flags,
2019 pr_warn("Unable to register %s clk\n", aux_clk->name);
2023 if (aux_clk->idx != NO_IDX)
2024 clks[aux_clk->idx] = hw;
2027 if (of_device_is_compatible(np, "st,stm32f746-rcc")) {
2045 CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
2046 CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
2047 CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init);
2048 CLK_OF_DECLARE_DRIVER(stm32f769_rcc, "st,stm32f769-rcc", stm32f4_rcc_init);