Lines Matching +full:clkout +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * clk-si5351.c: Skyworks / Silicon Labs Si5351A/B/C I2C Clock Generator
6 * Rabeeh Khoury <rabeeh@solid-run.com>
10 * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/data-sheets/Si5351-B.pdf
12 * https://www.skyworksinc.com/-/media/Skyworks/SL/documents/public/application-notes/AN619.pdf
18 #include <linux/clk-provider.h>
31 #include "clk-si5351.h"
63 struct si5351_hw_data *clkout; member
88 ret = regmap_read(drvdata->regmap, reg, &val); in si5351_reg_read()
90 dev_err(&drvdata->client->dev, in si5351_reg_read()
101 return regmap_bulk_read(drvdata->regmap, reg, buf, count); in si5351_bulk_read()
107 return regmap_write(drvdata->regmap, reg, val); in si5351_reg_write()
113 return regmap_raw_write(drvdata->regmap, reg, buf, count); in si5351_bulk_write()
119 return regmap_update_bits(drvdata->regmap, reg, mask, val); in si5351_set_bits()
125 return SI5351_CLK6_PARAMETERS + (num - 6); in si5351_msynth_params_address()
138 params->p1 = buf[0]; in si5351_read_parameters()
139 params->p2 = 0; in si5351_read_parameters()
140 params->p3 = 1; in si5351_read_parameters()
144 params->p1 = ((buf[2] & 0x03) << 16) | (buf[3] << 8) | buf[4]; in si5351_read_parameters()
145 params->p2 = ((buf[5] & 0x0f) << 16) | (buf[6] << 8) | buf[7]; in si5351_read_parameters()
146 params->p3 = ((buf[5] & 0xf0) << 12) | (buf[0] << 8) | buf[1]; in si5351_read_parameters()
148 params->valid = 1; in si5351_read_parameters()
159 buf[0] = params->p1 & 0xff; in si5351_write_parameters()
163 buf[0] = ((params->p3 & 0x0ff00) >> 8) & 0xff; in si5351_write_parameters()
164 buf[1] = params->p3 & 0xff; in si5351_write_parameters()
167 buf[2] |= ((params->p1 & 0x30000) >> 16) & 0x03; in si5351_write_parameters()
168 buf[3] = ((params->p1 & 0x0ff00) >> 8) & 0xff; in si5351_write_parameters()
169 buf[4] = params->p1 & 0xff; in si5351_write_parameters()
170 buf[5] = ((params->p3 & 0xf0000) >> 12) | in si5351_write_parameters()
171 ((params->p2 & 0xf0000) >> 16); in si5351_write_parameters()
172 buf[6] = ((params->p2 & 0x0ff00) >> 8) & 0xff; in si5351_write_parameters()
173 buf[7] = params->p2 & 0xff; in si5351_write_parameters()
200 /* read-only */ in si5351_regmap_is_writeable()
216 * Si5351 xtal clock input
241 * Si5351 clkin clock input (Si5351C only)
261 * CMOS clock source constraints:
290 dev_dbg(&drvdata->client->dev, "%s - clkin div = %d, rate = %lu\n", in si5351_clkin_recalc_rate()
303 * Si5351 vxco clock input (Si5351B only)
311 dev_warn(&hwdata->drvdata->client->dev, "VXCO currently unsupported\n"); in si5351_vxco_prepare()
351 * (1) MSNx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
352 * (2) MSNx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
358 * MSNx_P1 = 128 * a + (128 * b/MSNx_P2)/c - 512
374 return -EINVAL; in _si5351_pll_reparent()
376 if (drvdata->variant != SI5351_VARIANT_C && in _si5351_pll_reparent()
378 return -EINVAL; in _si5351_pll_reparent()
389 u8 mask = (hwdata->num == 0) ? SI5351_PLLA_SOURCE : SI5351_PLLB_SOURCE; in si5351_pll_get_parent()
392 val = si5351_reg_read(hwdata->drvdata, SI5351_PLL_INPUT_SOURCE); in si5351_pll_get_parent()
402 if (hwdata->drvdata->variant != SI5351_VARIANT_C && in si5351_pll_set_parent()
404 return -EPERM; in si5351_pll_set_parent()
407 return -EINVAL; in si5351_pll_set_parent()
409 return _si5351_pll_reparent(hwdata->drvdata, hwdata->num, in si5351_pll_set_parent()
419 u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : in si5351_pll_recalc_rate()
423 if (!hwdata->params.valid) in si5351_pll_recalc_rate()
424 si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params); in si5351_pll_recalc_rate()
426 if (hwdata->params.p3 == 0) in si5351_pll_recalc_rate()
430 rate = hwdata->params.p1 * hwdata->params.p3; in si5351_pll_recalc_rate()
431 rate += 512 * hwdata->params.p3; in si5351_pll_recalc_rate()
432 rate += hwdata->params.p2; in si5351_pll_recalc_rate()
434 do_div(rate, 128 * hwdata->params.p3); in si5351_pll_recalc_rate()
436 dev_dbg(&hwdata->drvdata->client->dev, in si5351_pll_recalc_rate()
437 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", in si5351_pll_recalc_rate()
439 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, in si5351_pll_recalc_rate()
450 unsigned long rate = req->rate; in si5351_pll_determine_rate()
460 a = rate / req->best_parent_rate; in si5351_pll_determine_rate()
463 rate = req->best_parent_rate * SI5351_PLL_A_MIN; in si5351_pll_determine_rate()
465 rate = req->best_parent_rate * SI5351_PLL_A_MAX; in si5351_pll_determine_rate()
469 lltmp = rate % (req->best_parent_rate); in si5351_pll_determine_rate()
471 do_div(lltmp, req->best_parent_rate); in si5351_pll_determine_rate()
481 hwdata->params.p3 = c; in si5351_pll_determine_rate()
482 hwdata->params.p2 = (128 * b) % c; in si5351_pll_determine_rate()
483 hwdata->params.p1 = 128 * a; in si5351_pll_determine_rate()
484 hwdata->params.p1 += (128 * b / c); in si5351_pll_determine_rate()
485 hwdata->params.p1 -= 512; in si5351_pll_determine_rate()
488 lltmp = req->best_parent_rate; in si5351_pll_determine_rate()
493 rate += req->best_parent_rate * a; in si5351_pll_determine_rate()
495 dev_dbg(&hwdata->drvdata->client->dev, in si5351_pll_determine_rate()
496 "%s - %s: a = %lu, b = %lu, c = %lu, parent_rate = %lu, rate = %lu\n", in si5351_pll_determine_rate()
498 req->best_parent_rate, rate); in si5351_pll_determine_rate()
500 req->rate = rate; in si5351_pll_determine_rate()
510 hwdata->drvdata->client->dev.platform_data; in si5351_pll_set_rate()
511 u8 reg = (hwdata->num == 0) ? SI5351_PLLA_PARAMETERS : in si5351_pll_set_rate()
515 si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params); in si5351_pll_set_rate()
518 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_CTRL + hwdata->num, in si5351_pll_set_rate()
520 (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); in si5351_pll_set_rate()
523 if (pdata->pll_reset[hwdata->num]) in si5351_pll_set_rate()
524 si5351_reg_write(hwdata->drvdata, SI5351_PLL_RESET, in si5351_pll_set_rate()
525 hwdata->num == 0 ? SI5351_PLL_RESET_A : in si5351_pll_set_rate()
528 dev_dbg(&hwdata->drvdata->client->dev, in si5351_pll_set_rate()
529 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, parent_rate = %lu, rate = %lu\n", in si5351_pll_set_rate()
531 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, in si5351_pll_set_rate()
555 * Output Clock Multisynth Register Equations
557 * MSx_P1[17:0] = 128 * a + floor(128 * b/c) - 512
558 * MSx_P2[19:0] = 128 * b - c * floor(128 * b/c) = (128*b) mod c
575 return -EINVAL; in _si5351_msynth_reparent()
589 val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num); in si5351_msynth_get_parent()
599 return _si5351_msynth_reparent(hwdata->drvdata, hwdata->num, in si5351_msynth_set_parent()
609 u8 reg = si5351_msynth_params_address(hwdata->num); in si5351_msynth_recalc_rate()
613 if (!hwdata->params.valid) in si5351_msynth_recalc_rate()
614 si5351_read_parameters(hwdata->drvdata, reg, &hwdata->params); in si5351_msynth_recalc_rate()
617 * multisync0-5: fOUT = (128 * P3 * fIN) / (P1*P3 + P2 + 512*P3) in si5351_msynth_recalc_rate()
618 * multisync6-7: fOUT = fIN / P1 in si5351_msynth_recalc_rate()
621 if (hwdata->num > 5) { in si5351_msynth_recalc_rate()
622 m = hwdata->params.p1; in si5351_msynth_recalc_rate()
623 } else if (hwdata->params.p3 == 0) { in si5351_msynth_recalc_rate()
625 } else if ((si5351_reg_read(hwdata->drvdata, reg + 2) & in si5351_msynth_recalc_rate()
629 rate *= 128 * hwdata->params.p3; in si5351_msynth_recalc_rate()
630 m = hwdata->params.p1 * hwdata->params.p3; in si5351_msynth_recalc_rate()
631 m += hwdata->params.p2; in si5351_msynth_recalc_rate()
632 m += 512 * hwdata->params.p3; in si5351_msynth_recalc_rate()
639 dev_dbg(&hwdata->drvdata->client->dev, in si5351_msynth_recalc_rate()
640 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, m = %lu, parent_rate = %lu, rate = %lu\n", in si5351_msynth_recalc_rate()
642 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, in si5351_msynth_recalc_rate()
653 unsigned long rate = req->rate; in si5351_msynth_determine_rate()
658 /* multisync6-7 can only handle freqencies < 150MHz */ in si5351_msynth_determine_rate()
659 if (hwdata->num >= 6 && rate > SI5351_MULTISYNTH67_MAX_FREQ) in si5351_msynth_determine_rate()
688 req->best_parent_rate = a * rate; in si5351_msynth_determine_rate()
689 } else if (hwdata->num >= 6) { in si5351_msynth_determine_rate()
691 a = DIV_ROUND_CLOSEST(req->best_parent_rate, rate); in si5351_msynth_determine_rate()
709 a = req->best_parent_rate / rate; in si5351_msynth_determine_rate()
717 lltmp = req->best_parent_rate % rate; in si5351_msynth_determine_rate()
731 lltmp = req->best_parent_rate; in si5351_msynth_determine_rate()
738 hwdata->params.p3 = 1; in si5351_msynth_determine_rate()
739 hwdata->params.p2 = 0; in si5351_msynth_determine_rate()
740 hwdata->params.p1 = 0; in si5351_msynth_determine_rate()
741 } else if (hwdata->num >= 6) { in si5351_msynth_determine_rate()
742 hwdata->params.p3 = 0; in si5351_msynth_determine_rate()
743 hwdata->params.p2 = 0; in si5351_msynth_determine_rate()
744 hwdata->params.p1 = a; in si5351_msynth_determine_rate()
746 hwdata->params.p3 = c; in si5351_msynth_determine_rate()
747 hwdata->params.p2 = (128 * b) % c; in si5351_msynth_determine_rate()
748 hwdata->params.p1 = 128 * a; in si5351_msynth_determine_rate()
749 hwdata->params.p1 += (128 * b / c); in si5351_msynth_determine_rate()
750 hwdata->params.p1 -= 512; in si5351_msynth_determine_rate()
753 dev_dbg(&hwdata->drvdata->client->dev, in si5351_msynth_determine_rate()
754 "%s - %s: a = %lu, b = %lu, c = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n", in si5351_msynth_determine_rate()
756 req->best_parent_rate, rate); in si5351_msynth_determine_rate()
758 req->rate = rate; in si5351_msynth_determine_rate()
768 u8 reg = si5351_msynth_params_address(hwdata->num); in si5351_msynth_set_rate()
772 si5351_write_parameters(hwdata->drvdata, reg, &hwdata->params); in si5351_msynth_set_rate()
777 /* enable/disable integer mode and divby4 on multisynth0-5 */ in si5351_msynth_set_rate()
778 if (hwdata->num < 6) { in si5351_msynth_set_rate()
779 si5351_set_bits(hwdata->drvdata, reg + 2, in si5351_msynth_set_rate()
782 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, in si5351_msynth_set_rate()
784 (hwdata->params.p2 == 0) ? SI5351_CLK_INTEGER_MODE : 0); in si5351_msynth_set_rate()
787 dev_dbg(&hwdata->drvdata->client->dev, in si5351_msynth_set_rate()
788 "%s - %s: p1 = %lu, p2 = %lu, p3 = %lu, divby4 = %d, parent_rate = %lu, rate = %lu\n", in si5351_msynth_set_rate()
790 hwdata->params.p1, hwdata->params.p2, hwdata->params.p3, in si5351_msynth_set_rate()
805 * Si5351 clkout divider
813 return -EINVAL; in _si5351_clkout_reparent()
830 if (drvdata->variant != SI5351_VARIANT_C) in _si5351_clkout_reparent()
831 return -EINVAL; in _si5351_clkout_reparent()
851 return -EINVAL; in _si5351_clkout_set_drive_strength()
881 u8 shift = (num < 4) ? (2 * num) : (2 * (num-4)); in _si5351_clkout_set_disable_state()
886 return -EINVAL; in _si5351_clkout_set_disable_state()
926 err = regmap_read_poll_timeout(drvdata->regmap, SI5351_PLL_RESET, v, in _si5351_clkout_reset_pll()
929 dev_err(&drvdata->client->dev, "Reset bit didn't clear\n"); in _si5351_clkout_reset_pll()
931 dev_dbg(&drvdata->client->dev, "%s - %s: pll = %d\n", in _si5351_clkout_reset_pll()
932 __func__, clk_hw_get_name(&drvdata->clkout[num].hw), in _si5351_clkout_reset_pll()
941 hwdata->drvdata->client->dev.platform_data; in si5351_clkout_prepare()
943 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, in si5351_clkout_prepare()
947 * Do a pll soft reset on the parent pll -- needed to get a in si5351_clkout_prepare()
950 if (pdata->clkout[hwdata->num].pll_reset) in si5351_clkout_prepare()
951 _si5351_clkout_reset_pll(hwdata->drvdata, hwdata->num); in si5351_clkout_prepare()
953 si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, in si5351_clkout_prepare()
954 (1 << hwdata->num), 0); in si5351_clkout_prepare()
963 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, in si5351_clkout_unprepare()
965 si5351_set_bits(hwdata->drvdata, SI5351_OUTPUT_ENABLE_CTRL, in si5351_clkout_unprepare()
966 (1 << hwdata->num), (1 << hwdata->num)); in si5351_clkout_unprepare()
976 val = si5351_reg_read(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num); in si5351_clkout_get_parent()
1016 return _si5351_clkout_reparent(hwdata->drvdata, hwdata->num, parent); in si5351_clkout_set_parent()
1027 if (hwdata->num <= 5) in si5351_clkout_recalc_rate()
1028 reg = si5351_msynth_params_address(hwdata->num) + 2; in si5351_clkout_recalc_rate()
1032 rdiv = si5351_reg_read(hwdata->drvdata, reg); in si5351_clkout_recalc_rate()
1033 if (hwdata->num == 6) { in si5351_clkout_recalc_rate()
1048 unsigned long rate = req->rate; in si5351_clkout_determine_rate()
1052 if (hwdata->num >= 6 && rate > SI5351_CLKOUT67_MAX_FREQ) in si5351_clkout_determine_rate()
1055 /* clkout freqency is 8kHz - 160MHz */ in si5351_clkout_determine_rate()
1070 req->best_parent_rate = rate; in si5351_clkout_determine_rate()
1076 new_rate = req->best_parent_rate; in si5351_clkout_determine_rate()
1077 err = abs(new_rate - rate); in si5351_clkout_determine_rate()
1080 new_err = abs(new_rate - rate); in si5351_clkout_determine_rate()
1087 rate = req->best_parent_rate >> rdiv; in si5351_clkout_determine_rate()
1089 dev_dbg(&hwdata->drvdata->client->dev, in si5351_clkout_determine_rate()
1090 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", in si5351_clkout_determine_rate()
1092 req->best_parent_rate, rate); in si5351_clkout_determine_rate()
1094 req->rate = rate; in si5351_clkout_determine_rate()
1109 err = abs(new_rate - rate); in si5351_clkout_set_rate()
1112 new_err = abs(new_rate - rate); in si5351_clkout_set_rate()
1120 switch (hwdata->num) { in si5351_clkout_set_rate()
1122 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER, in si5351_clkout_set_rate()
1126 si5351_set_bits(hwdata->drvdata, SI5351_CLK6_7_OUTPUT_DIVIDER, in si5351_clkout_set_rate()
1131 si5351_set_bits(hwdata->drvdata, in si5351_clkout_set_rate()
1132 si5351_msynth_params_address(hwdata->num) + 2, in si5351_clkout_set_rate()
1137 /* powerup clkout */ in si5351_clkout_set_rate()
1138 si5351_set_bits(hwdata->drvdata, SI5351_CLK0_CTRL + hwdata->num, in si5351_clkout_set_rate()
1141 dev_dbg(&hwdata->drvdata->client->dev, in si5351_clkout_set_rate()
1142 "%s - %s: rdiv = %u, parent_rate = %lu, rate = %lu\n", in si5351_clkout_set_rate()
1165 { .compatible = "silabs,si5351a-msop",
1176 struct device_node *child, *np = client->dev.of_node; in si5351_dt_parse()
1186 pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL); in si5351_dt_parse()
1188 return -ENOMEM; in si5351_dt_parse()
1191 * property silabs,pll-source : <num src>, [<..>] in si5351_dt_parse()
1194 sz = of_property_read_variable_u32_array(np, "silabs,pll-source", array, 2, 4); in si5351_dt_parse()
1195 sz = (sz == -EINVAL) ? 0 : sz; /* Missing property is OK */ in si5351_dt_parse()
1197 return dev_err_probe(&client->dev, sz, "invalid pll-source\n"); in si5351_dt_parse()
1199 return dev_err_probe(&client->dev, -EINVAL, in si5351_dt_parse()
1200 "missing pll-source for pll %d\n", array[sz - 1]); in si5351_dt_parse()
1207 dev_err(&client->dev, in si5351_dt_parse()
1208 "invalid pll %d on pll-source prop\n", num); in si5351_dt_parse()
1209 return -EINVAL; in si5351_dt_parse()
1214 pdata->pll_src[num] = SI5351_PLL_SRC_XTAL; in si5351_dt_parse()
1218 dev_err(&client->dev, in si5351_dt_parse()
1221 return -EINVAL; in si5351_dt_parse()
1223 pdata->pll_src[num] = SI5351_PLL_SRC_CLKIN; in si5351_dt_parse()
1226 dev_err(&client->dev, in si5351_dt_parse()
1228 return -EINVAL; in si5351_dt_parse()
1236 pdata->pll_reset[0] = true; in si5351_dt_parse()
1237 pdata->pll_reset[1] = true; in si5351_dt_parse()
1239 sz = of_property_read_variable_u32_array(np, "silabs,pll-reset-mode", array, 2, 4); in si5351_dt_parse()
1240 sz = (sz == -EINVAL) ? 0 : sz; /* Missing property is OK */ in si5351_dt_parse()
1242 return dev_err_probe(&client->dev, sz, "invalid pll-reset-mode\n"); in si5351_dt_parse()
1244 return dev_err_probe(&client->dev, -EINVAL, in si5351_dt_parse()
1245 "missing pll-reset-mode for pll %d\n", array[sz - 1]); in si5351_dt_parse()
1252 dev_err(&client->dev, in si5351_dt_parse()
1253 "invalid pll %d on pll-reset-mode prop\n", num); in si5351_dt_parse()
1254 return -EINVAL; in si5351_dt_parse()
1261 pdata->pll_reset[num] = true; in si5351_dt_parse()
1265 pdata->pll_reset[num] = false; in si5351_dt_parse()
1268 dev_err(&client->dev, in si5351_dt_parse()
1269 "invalid pll-reset-mode %d for pll %d\n", val, in si5351_dt_parse()
1271 return -EINVAL; in si5351_dt_parse()
1275 /* per clkout properties */ in si5351_dt_parse()
1278 dev_err(&client->dev, "missing reg property of %pOFn\n", in si5351_dt_parse()
1285 dev_err(&client->dev, "invalid clkout %d\n", num); in si5351_dt_parse()
1289 if (!of_property_read_u32(child, "silabs,multisynth-source", in si5351_dt_parse()
1293 pdata->clkout[num].multisynth_src = in si5351_dt_parse()
1297 pdata->clkout[num].multisynth_src = in si5351_dt_parse()
1301 dev_err(&client->dev, in si5351_dt_parse()
1308 if (!of_property_read_u32(child, "silabs,clock-source", &val)) { in si5351_dt_parse()
1311 pdata->clkout[num].clkout_src = in si5351_dt_parse()
1315 pdata->clkout[num].clkout_src = in si5351_dt_parse()
1319 pdata->clkout[num].clkout_src = in si5351_dt_parse()
1324 dev_err(&client->dev, in si5351_dt_parse()
1325 "invalid parent %d for clkout %d\n", in si5351_dt_parse()
1329 pdata->clkout[num].clkout_src = in si5351_dt_parse()
1333 dev_err(&client->dev, in si5351_dt_parse()
1334 "invalid parent %d for clkout %d\n", in si5351_dt_parse()
1340 if (!of_property_read_u32(child, "silabs,drive-strength", in si5351_dt_parse()
1347 pdata->clkout[num].drive = val; in si5351_dt_parse()
1350 dev_err(&client->dev, in si5351_dt_parse()
1351 "invalid drive strength %d for clkout %d\n", in si5351_dt_parse()
1357 if (!of_property_read_u32(child, "silabs,disable-state", in si5351_dt_parse()
1361 pdata->clkout[num].disable_state = in si5351_dt_parse()
1365 pdata->clkout[num].disable_state = in si5351_dt_parse()
1369 pdata->clkout[num].disable_state = in si5351_dt_parse()
1373 pdata->clkout[num].disable_state = in si5351_dt_parse()
1377 dev_err(&client->dev, in si5351_dt_parse()
1378 "invalid disable state %d for clkout %d\n", in si5351_dt_parse()
1384 if (!of_property_read_u32(child, "clock-frequency", &val)) in si5351_dt_parse()
1385 pdata->clkout[num].rate = val; in si5351_dt_parse()
1387 pdata->clkout[num].pll_master = in si5351_dt_parse()
1388 of_property_read_bool(child, "silabs,pll-master"); in si5351_dt_parse()
1390 pdata->clkout[num].pll_reset = in si5351_dt_parse()
1391 of_property_read_bool(child, "silabs,pll-reset"); in si5351_dt_parse()
1393 client->dev.platform_data = pdata; in si5351_dt_parse()
1398 return -EINVAL; in si5351_dt_parse()
1405 unsigned int idx = clkspec->args[0]; in si53351_of_clk_get()
1407 if (idx >= drvdata->num_clkout) { in si53351_of_clk_get()
1409 return ERR_PTR(-EINVAL); in si53351_of_clk_get()
1412 return &drvdata->clkout[idx].hw; in si53351_of_clk_get()
1429 { "si5351a-msop", SI5351_VARIANT_A3 },
1451 pdata = client->dev.platform_data; in si5351_i2c_probe()
1453 return -EINVAL; in si5351_i2c_probe()
1455 drvdata = devm_kzalloc(&client->dev, sizeof(*drvdata), GFP_KERNEL); in si5351_i2c_probe()
1457 return -ENOMEM; in si5351_i2c_probe()
1460 drvdata->client = client; in si5351_i2c_probe()
1461 drvdata->variant = variant; in si5351_i2c_probe()
1462 drvdata->pxtal = devm_clk_get(&client->dev, "xtal"); in si5351_i2c_probe()
1463 drvdata->pclkin = devm_clk_get(&client->dev, "clkin"); in si5351_i2c_probe()
1465 if (PTR_ERR(drvdata->pxtal) == -EPROBE_DEFER || in si5351_i2c_probe()
1466 PTR_ERR(drvdata->pclkin) == -EPROBE_DEFER) in si5351_i2c_probe()
1467 return -EPROBE_DEFER; in si5351_i2c_probe()
1470 * Check for valid parent clock: VARIANT_A and VARIANT_B need XTAL, in si5351_i2c_probe()
1473 if (IS_ERR(drvdata->pxtal) && in si5351_i2c_probe()
1474 (drvdata->variant != SI5351_VARIANT_C || IS_ERR(drvdata->pclkin))) { in si5351_i2c_probe()
1475 dev_err(&client->dev, "missing parent clock\n"); in si5351_i2c_probe()
1476 return -EINVAL; in si5351_i2c_probe()
1479 drvdata->regmap = devm_regmap_init_i2c(client, &si5351_regmap_config); in si5351_i2c_probe()
1480 if (IS_ERR(drvdata->regmap)) { in si5351_i2c_probe()
1481 dev_err(&client->dev, "failed to allocate register map\n"); in si5351_i2c_probe()
1482 return PTR_ERR(drvdata->regmap); in si5351_i2c_probe()
1488 if (drvdata->variant != SI5351_VARIANT_C) in si5351_i2c_probe()
1492 /* setup clock configuration */ in si5351_i2c_probe()
1494 ret = _si5351_pll_reparent(drvdata, n, pdata->pll_src[n]); in si5351_i2c_probe()
1496 dev_err(&client->dev, in si5351_i2c_probe()
1498 n, pdata->pll_src[n]); in si5351_i2c_probe()
1505 pdata->clkout[n].multisynth_src); in si5351_i2c_probe()
1507 dev_err(&client->dev, in si5351_i2c_probe()
1509 n, pdata->clkout[n].multisynth_src); in si5351_i2c_probe()
1514 pdata->clkout[n].clkout_src); in si5351_i2c_probe()
1516 dev_err(&client->dev, in si5351_i2c_probe()
1517 "failed to reparent clkout %d to %d\n", in si5351_i2c_probe()
1518 n, pdata->clkout[n].clkout_src); in si5351_i2c_probe()
1523 pdata->clkout[n].drive); in si5351_i2c_probe()
1525 dev_err(&client->dev, in si5351_i2c_probe()
1526 "failed set drive strength of clkout%d to %d\n", in si5351_i2c_probe()
1527 n, pdata->clkout[n].drive); in si5351_i2c_probe()
1532 pdata->clkout[n].disable_state); in si5351_i2c_probe()
1534 dev_err(&client->dev, in si5351_i2c_probe()
1535 "failed set disable state of clkout%d to %d\n", in si5351_i2c_probe()
1536 n, pdata->clkout[n].disable_state); in si5351_i2c_probe()
1541 /* register xtal input clock gate */ in si5351_i2c_probe()
1546 if (!IS_ERR(drvdata->pxtal)) { in si5351_i2c_probe()
1547 drvdata->pxtal_name = __clk_get_name(drvdata->pxtal); in si5351_i2c_probe()
1548 init.parent_names = &drvdata->pxtal_name; in si5351_i2c_probe()
1551 drvdata->xtal.init = &init; in si5351_i2c_probe()
1552 ret = devm_clk_hw_register(&client->dev, &drvdata->xtal); in si5351_i2c_probe()
1554 dev_err(&client->dev, "unable to register %s\n", init.name); in si5351_i2c_probe()
1558 /* register clkin input clock gate */ in si5351_i2c_probe()
1559 if (drvdata->variant == SI5351_VARIANT_C) { in si5351_i2c_probe()
1563 if (!IS_ERR(drvdata->pclkin)) { in si5351_i2c_probe()
1564 drvdata->pclkin_name = __clk_get_name(drvdata->pclkin); in si5351_i2c_probe()
1565 init.parent_names = &drvdata->pclkin_name; in si5351_i2c_probe()
1568 drvdata->clkin.init = &init; in si5351_i2c_probe()
1569 ret = devm_clk_hw_register(&client->dev, &drvdata->clkin); in si5351_i2c_probe()
1571 dev_err(&client->dev, "unable to register %s\n", in si5351_i2c_probe()
1578 num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 2 : 1; in si5351_i2c_probe()
1583 drvdata->pll[0].num = 0; in si5351_i2c_probe()
1584 drvdata->pll[0].drvdata = drvdata; in si5351_i2c_probe()
1585 drvdata->pll[0].hw.init = &init; in si5351_i2c_probe()
1592 ret = devm_clk_hw_register(&client->dev, &drvdata->pll[0].hw); in si5351_i2c_probe()
1594 dev_err(&client->dev, "unable to register %s\n", init.name); in si5351_i2c_probe()
1599 drvdata->pll[1].num = 1; in si5351_i2c_probe()
1600 drvdata->pll[1].drvdata = drvdata; in si5351_i2c_probe()
1601 drvdata->pll[1].hw.init = &init; in si5351_i2c_probe()
1603 if (drvdata->variant == SI5351_VARIANT_B) { in si5351_i2c_probe()
1616 ret = devm_clk_hw_register(&client->dev, &drvdata->pll[1].hw); in si5351_i2c_probe()
1618 dev_err(&client->dev, "unable to register %s\n", init.name); in si5351_i2c_probe()
1623 num_clocks = (drvdata->variant == SI5351_VARIANT_A3) ? 3 : 8; in si5351_i2c_probe()
1625 if (drvdata->variant == SI5351_VARIANT_B) in si5351_i2c_probe()
1630 drvdata->msynth = devm_kcalloc(&client->dev, num_clocks, in si5351_i2c_probe()
1631 sizeof(*drvdata->msynth), GFP_KERNEL); in si5351_i2c_probe()
1632 drvdata->clkout = devm_kcalloc(&client->dev, num_clocks, in si5351_i2c_probe()
1633 sizeof(*drvdata->clkout), GFP_KERNEL); in si5351_i2c_probe()
1634 drvdata->num_clkout = num_clocks; in si5351_i2c_probe()
1636 if (WARN_ON(!drvdata->msynth || !drvdata->clkout)) { in si5351_i2c_probe()
1637 ret = -ENOMEM; in si5351_i2c_probe()
1642 drvdata->msynth[n].num = n; in si5351_i2c_probe()
1643 drvdata->msynth[n].drvdata = drvdata; in si5351_i2c_probe()
1644 drvdata->msynth[n].hw.init = &init; in si5351_i2c_probe()
1649 if (pdata->clkout[n].pll_master) in si5351_i2c_probe()
1653 ret = devm_clk_hw_register(&client->dev, in si5351_i2c_probe()
1654 &drvdata->msynth[n].hw); in si5351_i2c_probe()
1656 dev_err(&client->dev, "unable to register %s\n", in si5351_i2c_probe()
1662 num_parents = (drvdata->variant == SI5351_VARIANT_C) ? 4 : 3; in si5351_i2c_probe()
1670 drvdata->clkout[n].num = n; in si5351_i2c_probe()
1671 drvdata->clkout[n].drvdata = drvdata; in si5351_i2c_probe()
1672 drvdata->clkout[n].hw.init = &init; in si5351_i2c_probe()
1677 if (pdata->clkout[n].clkout_src == SI5351_CLKOUT_SRC_MSYNTH_N) in si5351_i2c_probe()
1681 ret = devm_clk_hw_register(&client->dev, in si5351_i2c_probe()
1682 &drvdata->clkout[n].hw); in si5351_i2c_probe()
1684 dev_err(&client->dev, "unable to register %s\n", in si5351_i2c_probe()
1689 /* set initial clkout rate */ in si5351_i2c_probe()
1690 if (pdata->clkout[n].rate != 0) { in si5351_i2c_probe()
1692 ret = clk_set_rate(drvdata->clkout[n].hw.clk, in si5351_i2c_probe()
1693 pdata->clkout[n].rate); in si5351_i2c_probe()
1695 dev_err(&client->dev, "Cannot set rate : %d\n", in si5351_i2c_probe()
1701 ret = devm_of_clk_add_hw_provider(&client->dev, si53351_of_clk_get, in si5351_i2c_probe()
1704 dev_err(&client->dev, "unable to add clk provider\n"); in si5351_i2c_probe()
1722 MODULE_DESCRIPTION("Silicon Labs Si5351A/B/C clock generator driver");