Lines Matching +full:xaxb +full:- +full:ext +full:- +full:clk
1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
74 struct clk_si5341_output clk[SI5341_MAX_NUM_OUTPUTS]; member
75 struct clk *input_clk[SI5341_NUM_INPUTS];
127 /* Input dividers (48-bit) */
138 ((output)->data->reg_output_offset[(output)->index])
143 ((output)->data->reg_rdiv_offset[(output)->index])
220 * using only the XTAL input, without pre-divider.
364 /* Read and interpret a 44-bit followed by a 32-bit value in the regmap */
416 err = si5341_decode_44_32(data->regmap, SI5341_PLL_M_NUM, in si5341_clk_recalc_rate()
425 * Though m_num is 64-bit, only the upper bits are actually used. While in si5341_clk_recalc_rate()
427 * the left. To avoid 96-bit division here, we just shift them back so in si5341_clk_recalc_rate()
440 data->freq_vco = res; in si5341_clk_recalc_rate()
453 err = regmap_read(data->regmap, SI5341_IN_SEL, &val); in si5341_clk_get_selected_input()
477 /* Enable register-based input selection */ in si5341_clk_reparent()
480 err = regmap_update_bits(data->regmap, in si5341_clk_reparent()
487 err = regmap_update_bits(data->regmap, in si5341_clk_reparent()
493 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN, in si5341_clk_reparent()
500 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG, in si5341_clk_reparent()
510 err = regmap_write(data->regmap, SI5341_IN_PDIV(index), 1); in si5341_clk_reparent()
514 err = regmap_write(data->regmap, SI5341_IN_PSET(index), 1); in si5341_clk_reparent()
519 err = regmap_write(data->regmap, SI5341_PX_UPD, BIT(index)); in si5341_clk_reparent()
524 err = regmap_update_bits(data->regmap, SI5341_IN_EN, 0x07, 0); in si5341_clk_reparent()
529 err = regmap_update_bits(data->regmap, SI5341_INX_TO_PFD_EN, in si5341_clk_reparent()
535 err = regmap_update_bits(data->regmap, SI5341_XAXB_CFG, in si5341_clk_reparent()
537 SI5341_XAXB_CFG_PDNB | (data->xaxb_ext_clk ? in si5341_clk_reparent()
568 u8 index = synth->index; in si5341_synth_clk_is_on()
570 err = regmap_read(synth->data->regmap, in si5341_synth_clk_is_on()
578 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_PDNB, &val); in si5341_synth_clk_is_on()
586 err = regmap_read(synth->data->regmap, SI5341_SYNTH_N_CLK_DIS, &val); in si5341_synth_clk_is_on()
596 u8 index = synth->index; /* In range 0..5 */ in si5341_synth_clk_unprepare()
600 regmap_update_bits(synth->data->regmap, in si5341_synth_clk_unprepare()
603 regmap_update_bits(synth->data->regmap, in si5341_synth_clk_unprepare()
606 regmap_update_bits(synth->data->regmap, in si5341_synth_clk_unprepare()
614 u8 index = synth->index; in si5341_synth_clk_prepare()
618 err = regmap_update_bits(synth->data->regmap, in si5341_synth_clk_prepare()
624 err = regmap_update_bits(synth->data->regmap, in si5341_synth_clk_prepare()
630 return regmap_update_bits(synth->data->regmap, in si5341_synth_clk_prepare()
634 /* Synth clock frequency: Fvco * n_den / n_den, with Fvco in 13500-14256 MHz */
644 err = si5341_decode_44_32(synth->data->regmap, in si5341_synth_clk_recalc_rate()
645 SI5341_SYNTH_N_NUM(synth->index), &n_num, &n_den); in si5341_synth_clk_recalc_rate()
654 * overflow in 64-bit math, we shift n_den 4 bits to the right in si5341_synth_clk_recalc_rate()
656 f = synth->data->freq_vco; in si5341_synth_clk_recalc_rate()
659 /* Now we need to do 64-bit division: f/n_num */ in si5341_synth_clk_recalc_rate()
673 f = synth->data->freq_vco; in si5341_synth_clk_determine_rate()
675 if (req->rate < f) { in si5341_synth_clk_determine_rate()
676 req->rate = f; in si5341_synth_clk_determine_rate()
681 f = synth->data->freq_vco; in si5341_synth_clk_determine_rate()
683 if (req->rate > f) { in si5341_synth_clk_determine_rate()
684 req->rate = f; in si5341_synth_clk_determine_rate()
696 u8 index = synth->index; in si5341_synth_program()
698 err = si5341_encode_44_32(synth->data->regmap, in si5341_synth_program()
701 err = regmap_update_bits(synth->data->regmap, in si5341_synth_program()
706 return regmap_write(synth->data->regmap, in si5341_synth_program()
721 n_num = synth->data->freq_vco; in si5341_synth_clk_set_rate()
737 dev_dbg(&synth->data->i2c_client->dev, in si5341_synth_clk_set_rate()
739 synth->index, n_num, n_den, in si5341_synth_clk_set_rate()
760 err = regmap_read(output->data->regmap, in si5341_output_clk_is_on()
774 regmap_update_bits(output->data->regmap, in si5341_output_clk_unprepare()
777 regmap_update_bits(output->data->regmap, in si5341_output_clk_unprepare()
788 err = regmap_update_bits(output->data->regmap, in si5341_output_clk_prepare()
794 return regmap_update_bits(output->data->regmap, in si5341_output_clk_prepare()
808 err = regmap_read(output->data->regmap, in si5341_output_clk_recalc_rate()
817 err = regmap_bulk_read(output->data->regmap, in si5341_output_clk_recalc_rate()
822 /* Calculate value as 24-bit integer*/ in si5341_output_clk_recalc_rate()
840 unsigned long rate = req->rate; in si5341_output_clk_determine_rate()
846 r = req->best_parent_rate >> 1; in si5341_output_clk_determine_rate()
854 /* minimum r-divider is 2 */ in si5341_output_clk_determine_rate()
860 req->best_parent_rate = r * rate; in si5341_output_clk_determine_rate()
864 rate = req->best_parent_rate / (r << 1); in si5341_output_clk_determine_rate()
867 req->rate = rate; in si5341_output_clk_determine_rate()
880 return -EINVAL; in si5341_output_clk_set_rate()
888 r_div = BIT(24) - 1; in si5341_output_clk_set_rate()
890 --r_div; in si5341_output_clk_set_rate()
893 err = regmap_update_bits(output->data->regmap, in si5341_output_clk_set_rate()
904 return regmap_bulk_write(output->data->regmap, in si5341_output_clk_set_rate()
910 return regmap_update_bits(output->data->regmap, in si5341_output_reparent()
918 if (index >= output->data->num_synth) in si5341_output_set_parent()
919 return -EINVAL; in si5341_output_set_parent()
929 regmap_read(output->data->regmap, SI5341_OUT_MUX_SEL(output), &val); in si5341_output_get_parent()
946 * The chip can be bought in a pre-programmed version, or one can program the
956 /* Read the PLL divider value, it must have a non-zero value */ in si5341_is_programmed_already()
957 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_DEN, in si5341_is_programmed_already()
969 unsigned int idx = clkspec->args[1]; in of_clk_si5341_get()
970 unsigned int group = clkspec->args[0]; in of_clk_si5341_get()
974 if (idx >= data->num_outputs) { in of_clk_si5341_get()
975 dev_err(&data->i2c_client->dev, in of_clk_si5341_get()
977 return ERR_PTR(-EINVAL); in of_clk_si5341_get()
979 return &data->clk[idx].hw; in of_clk_si5341_get()
981 if (idx >= data->num_synth) { in of_clk_si5341_get()
982 dev_err(&data->i2c_client->dev, in of_clk_si5341_get()
984 return ERR_PTR(-EINVAL); in of_clk_si5341_get()
986 return &data->synth[idx].hw; in of_clk_si5341_get()
989 dev_err(&data->i2c_client->dev, in of_clk_si5341_get()
991 return ERR_PTR(-EINVAL); in of_clk_si5341_get()
993 return &data->hw; in of_clk_si5341_get()
995 dev_err(&data->i2c_client->dev, "invalid group %u\n", group); in of_clk_si5341_get()
996 return ERR_PTR(-EINVAL); in of_clk_si5341_get()
1006 err = regmap_bulk_read(data->regmap, SI5341_PN_BASE, reg, in si5341_probe_chip_id()
1009 dev_err(&data->i2c_client->dev, "Failed to read chip ID\n"); in si5341_probe_chip_id()
1015 dev_info(&data->i2c_client->dev, "Chip: %x Grade: %u Rev: %u\n", in si5341_probe_chip_id()
1020 data->num_outputs = SI5340_MAX_NUM_OUTPUTS; in si5341_probe_chip_id()
1021 data->num_synth = SI5340_NUM_SYNTH; in si5341_probe_chip_id()
1022 data->reg_output_offset = si5340_reg_output_offset; in si5341_probe_chip_id()
1023 data->reg_rdiv_offset = si5340_reg_rdiv_offset; in si5341_probe_chip_id()
1026 data->num_outputs = SI5341_MAX_NUM_OUTPUTS; in si5341_probe_chip_id()
1027 data->num_synth = SI5341_NUM_SYNTH; in si5341_probe_chip_id()
1028 data->reg_output_offset = si5341_reg_output_offset; in si5341_probe_chip_id()
1029 data->reg_rdiv_offset = si5341_reg_rdiv_offset; in si5341_probe_chip_id()
1032 data->num_outputs = SI5342_MAX_NUM_OUTPUTS; in si5341_probe_chip_id()
1033 data->num_synth = SI5342_NUM_SYNTH; in si5341_probe_chip_id()
1034 data->reg_output_offset = si5340_reg_output_offset; in si5341_probe_chip_id()
1035 data->reg_rdiv_offset = si5340_reg_rdiv_offset; in si5341_probe_chip_id()
1038 data->num_outputs = SI5344_MAX_NUM_OUTPUTS; in si5341_probe_chip_id()
1039 data->num_synth = SI5344_NUM_SYNTH; in si5341_probe_chip_id()
1040 data->reg_output_offset = si5340_reg_output_offset; in si5341_probe_chip_id()
1041 data->reg_rdiv_offset = si5340_reg_rdiv_offset; in si5341_probe_chip_id()
1044 data->num_outputs = SI5345_MAX_NUM_OUTPUTS; in si5341_probe_chip_id()
1045 data->num_synth = SI5345_NUM_SYNTH; in si5341_probe_chip_id()
1046 data->reg_output_offset = si5341_reg_output_offset; in si5341_probe_chip_id()
1047 data->reg_rdiv_offset = si5341_reg_rdiv_offset; in si5341_probe_chip_id()
1050 dev_err(&data->i2c_client->dev, "Model '%x' not supported\n", in si5341_probe_chip_id()
1052 return -EINVAL; in si5341_probe_chip_id()
1055 data->chip_id = model; in si5341_probe_chip_id()
1067 err = regmap_bulk_read(data->regmap, SI5341_PLL_M_NUM, r, 10); in si5341_read_settings()
1071 err = regmap_bulk_read(data->regmap, in si5341_read_settings()
1076 err = regmap_bulk_read(data->regmap, in si5341_read_settings()
1081 for (i = 0; i < data->num_synth; ++i) { in si5341_read_settings()
1082 err = regmap_bulk_read(data->regmap, in si5341_read_settings()
1088 for (i = 0; i < data->num_outputs; ++i) { in si5341_read_settings()
1089 err = regmap_bulk_read(data->regmap, in si5341_read_settings()
1090 data->reg_output_offset[i], r, 4); in si5341_read_settings()
1094 err = regmap_bulk_read(data->regmap, in si5341_read_settings()
1095 data->reg_rdiv_offset[i], r, 3); in si5341_read_settings()
1110 res = regmap_write(data->regmap, in si5341_write_multiple()
1113 dev_err(&data->i2c_client->dev, in si5341_write_multiple()
1142 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); in si5341_send_preamble()
1147 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xD8 : 0xC0); in si5341_send_preamble()
1152 if (data->chip_id > 0x5341) in si5341_send_preamble()
1167 /* Perform a soft reset and write post-amble */
1173 res = regmap_write(data->regmap, SI5341_IO_VDD_SEL, in si5341_finalize_defaults()
1174 data->iovdd_33 ? 1 : 0); in si5341_finalize_defaults()
1178 res = regmap_read(data->regmap, SI5341_DEVICE_REV, &revision); in si5341_finalize_defaults()
1182 dev_dbg(&data->i2c_client->dev, "%s rev=%u\n", __func__, revision); in si5341_finalize_defaults()
1184 res = regmap_write(data->regmap, SI5341_SOFT_RST, 0x01); in si5341_finalize_defaults()
1188 /* The si5342..si5345 have an additional post-amble */ in si5341_finalize_defaults()
1189 if (data->chip_id > 0x5341) { in si5341_finalize_defaults()
1190 res = regmap_write(data->regmap, 0x540, 0x0); in si5341_finalize_defaults()
1196 res = regmap_write(data->regmap, 0xB24, revision < 2 ? 0xDB : 0xC3); in si5341_finalize_defaults()
1199 res = regmap_write(data->regmap, 0x0B25, 0x02); in si5341_finalize_defaults()
1260 dev_err(&client->dev, "timeout waiting for DEVICE_READY\n"); in si5341_wait_device_ready()
1261 return -EIO; in si5341_wait_device_ready()
1278 struct device_node *np = data->i2c_client->dev.of_node; in si5341_dt_parse_dt()
1287 dev_err(&data->i2c_client->dev, "missing reg property of %s\n", in si5341_dt_parse_dt()
1288 child->name); in si5341_dt_parse_dt()
1293 dev_err(&data->i2c_client->dev, "invalid clkout %d\n", num); in si5341_dt_parse_dt()
1303 case 2: /* low-power differential */ in si5341_dt_parse_dt()
1312 dev_err(&data->i2c_client->dev, in si5341_dt_parse_dt()
1323 if (!of_property_read_u32(child, "silabs,common-mode", &val)) { in si5341_dt_parse_dt()
1325 dev_err(&data->i2c_client->dev, in si5341_dt_parse_dt()
1326 "invalid silabs,common-mode %u\n", in si5341_dt_parse_dt()
1336 dev_err(&data->i2c_client->dev, in si5341_dt_parse_dt()
1345 if (of_property_read_bool(child, "silabs,disable-high")) in si5341_dt_parse_dt()
1349 of_property_read_bool(child, "silabs,synth-master"); in si5341_dt_parse_dt()
1352 of_property_read_bool(child, "always-on"); in si5341_dt_parse_dt()
1355 if (data->clk[num].vddo_reg) { in si5341_dt_parse_dt()
1356 int vdd = regulator_get_voltage(data->clk[num].vddo_reg); in si5341_dt_parse_dt()
1369 dev_err(&data->i2c_client->dev, in si5341_dt_parse_dt()
1371 vdd, child->name); in si5341_dt_parse_dt()
1376 dev_warn(&data->i2c_client->dev, in si5341_dt_parse_dt()
1378 child->name); in si5341_dt_parse_dt()
1387 return -EINVAL; in si5341_dt_parse_dt()
1391 * If not pre-configured, calculate and set the PLL configuration manually.
1392 * For low-jitter performance, the PLL should be set such that the synthesizers
1396 * may be sub-optimal.
1400 struct device_node *np = data->i2c_client->dev.of_node; in si5341_initialize_pll()
1405 if (of_property_read_u32(np, "silabs,pll-m-num", &m_num)) { in si5341_initialize_pll()
1406 dev_err(&data->i2c_client->dev, in si5341_initialize_pll()
1407 "PLL configuration requires silabs,pll-m-num\n"); in si5341_initialize_pll()
1409 if (of_property_read_u32(np, "silabs,pll-m-den", &m_den)) { in si5341_initialize_pll()
1410 dev_err(&data->i2c_client->dev, in si5341_initialize_pll()
1411 "PLL configuration requires silabs,pll-m-den\n"); in si5341_initialize_pll()
1415 dev_err(&data->i2c_client->dev, in si5341_initialize_pll()
1421 m_den = clk_get_rate(data->input_clk[sel]) / 10; in si5341_initialize_pll()
1425 return si5341_encode_44_32(data->regmap, in si5341_initialize_pll()
1440 if (!data->input_clk[res]) { in si5341_clk_select_active_input()
1441 dev_dbg(&data->i2c_client->dev, in si5341_clk_select_active_input()
1443 res = -ENODEV; in si5341_clk_select_active_input()
1445 if (data->input_clk[i]) { in si5341_clk_select_active_input()
1451 dev_err(&data->i2c_client->dev, in si5341_clk_select_active_input()
1462 err = clk_prepare_enable(data->input_clk[res]); in si5341_clk_select_active_input()
1475 int res = regmap_read(data->regmap, SI5341_STATUS, &status); in input_present_show()
1490 int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status); in input_present_sticky_show()
1505 int res = regmap_read(data->regmap, SI5341_STATUS, &status); in pll_locked_show()
1520 int res = regmap_read(data->regmap, SI5341_STATUS_STICKY, &status); in pll_locked_sticky_show()
1537 return -EINVAL; in clear_sticky_store()
1539 int res = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0); in clear_sticky_store()
1561 struct clk *input; in si5341_probe()
1570 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); in si5341_probe()
1572 return -ENOMEM; in si5341_probe()
1574 data->i2c_client = client; in si5341_probe()
1582 input = devm_clk_get(&client->dev, si5341_input_clock_names[i]); in si5341_probe()
1584 if (PTR_ERR(input) == -EPROBE_DEFER) in si5341_probe()
1585 return -EPROBE_DEFER; in si5341_probe()
1586 data->input_clk_name[i] = si5341_input_clock_names[i]; in si5341_probe()
1588 data->input_clk[i] = input; in si5341_probe()
1589 data->input_clk_name[i] = __clk_get_name(input); in si5341_probe()
1597 data->clk[i].vddo_reg = devm_regulator_get_optional( in si5341_probe()
1598 &client->dev, reg_name); in si5341_probe()
1599 if (IS_ERR(data->clk[i].vddo_reg)) { in si5341_probe()
1600 err = PTR_ERR(data->clk[i].vddo_reg); in si5341_probe()
1601 data->clk[i].vddo_reg = NULL; in si5341_probe()
1602 if (err == -ENODEV) in si5341_probe()
1606 err = regulator_enable(data->clk[i].vddo_reg); in si5341_probe()
1608 dev_err(&client->dev, in si5341_probe()
1611 data->clk[i].vddo_reg = NULL; in si5341_probe()
1621 if (of_property_read_string(client->dev.of_node, "clock-output-names", in si5341_probe()
1623 init.name = client->dev.of_node->name; in si5341_probe()
1626 data->regmap = devm_regmap_init_i2c(client, &si5341_regmap_config); in si5341_probe()
1627 if (IS_ERR(data->regmap)) { in si5341_probe()
1628 err = PTR_ERR(data->regmap); in si5341_probe()
1638 if (of_property_read_bool(client->dev.of_node, "silabs,reprogram")) { in si5341_probe()
1647 data->xaxb_ext_clk = of_property_read_bool(client->dev.of_node, in si5341_probe()
1648 "silabs,xaxb-ext-clk"); in si5341_probe()
1649 data->iovdd_33 = of_property_read_bool(client->dev.of_node, in si5341_probe()
1650 "silabs,iovdd-33"); in si5341_probe()
1667 regcache_cache_only(data->regmap, true); in si5341_probe()
1689 init.parent_names = data->input_clk_name; in si5341_probe()
1693 data->hw.init = &init; in si5341_probe()
1695 err = devm_clk_hw_register(&client->dev, &data->hw); in si5341_probe()
1697 dev_err(&client->dev, "clock registration failed\n"); in si5341_probe()
1704 for (i = 0; i < data->num_synth; ++i) { in si5341_probe()
1705 synth_clock_names[i] = devm_kasprintf(&client->dev, GFP_KERNEL, in si5341_probe()
1706 "%s.N%u", client->dev.of_node->name, i); in si5341_probe()
1708 err = -ENOMEM; in si5341_probe()
1712 data->synth[i].index = i; in si5341_probe()
1713 data->synth[i].data = data; in si5341_probe()
1714 data->synth[i].hw.init = &init; in si5341_probe()
1715 err = devm_clk_hw_register(&client->dev, &data->synth[i].hw); in si5341_probe()
1717 dev_err(&client->dev, in si5341_probe()
1723 init.num_parents = data->num_synth; in si5341_probe()
1726 for (i = 0; i < data->num_outputs; ++i) { in si5341_probe()
1728 client->dev.of_node->name, i); in si5341_probe()
1730 err = -ENOMEM; in si5341_probe()
1734 data->clk[i].index = i; in si5341_probe()
1735 data->clk[i].data = data; in si5341_probe()
1736 data->clk[i].hw.init = &init; in si5341_probe()
1738 regmap_write(data->regmap, in si5341_probe()
1739 SI5341_OUT_FORMAT(&data->clk[i]), in si5341_probe()
1741 regmap_write(data->regmap, in si5341_probe()
1742 SI5341_OUT_CM(&data->clk[i]), in si5341_probe()
1744 regmap_update_bits(data->regmap, in si5341_probe()
1745 SI5341_OUT_MUX_SEL(&data->clk[i]), in si5341_probe()
1749 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); in si5341_probe()
1752 dev_err(&client->dev, in si5341_probe()
1757 clk_prepare(data->clk[i].hw.clk); in si5341_probe()
1760 err = devm_of_clk_add_hw_provider(&client->dev, of_clk_si5341_get, in si5341_probe()
1763 dev_err(&client->dev, "unable to add clk provider\n"); in si5341_probe()
1769 regcache_cache_only(data->regmap, false); in si5341_probe()
1770 err = regcache_sync(data->regmap); in si5341_probe()
1780 err = regmap_read_poll_timeout(data->regmap, SI5341_STATUS, status, in si5341_probe()
1784 dev_err(&client->dev, "Error waiting for input clock or PLL lock\n"); in si5341_probe()
1789 err = regmap_write(data->regmap, SI5341_STATUS_STICKY, 0); in si5341_probe()
1791 dev_err(&client->dev, "unable to clear sticky status\n"); in si5341_probe()
1795 err = sysfs_create_files(&client->dev.kobj, si5341_attributes); in si5341_probe()
1797 dev_err(&client->dev, "unable to create sysfs files\n"); in si5341_probe()
1800 /* Free the names, clk framework makes copies */ in si5341_probe()
1801 for (i = 0; i < data->num_synth; ++i) in si5341_probe()
1802 devm_kfree(&client->dev, (void *)synth_clock_names[i]); in si5341_probe()
1807 if (data->clk[i].vddo_reg) in si5341_probe()
1808 regulator_disable(data->clk[i].vddo_reg); in si5341_probe()
1819 sysfs_remove_files(&client->dev.kobj, si5341_attributes); in si5341_remove()
1822 if (data->clk[i].vddo_reg) in si5341_remove()
1823 regulator_disable(data->clk[i].vddo_reg); in si5341_remove()