Lines Matching refs:CGA_PLL1
30 #define CGA_PLL1 1 macro
124 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
125 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
132 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
140 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
141 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
148 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
156 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
157 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
165 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
166 [1] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV2 },
174 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
175 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
184 [0] = { CLKSEL_VALID | CLKSEL_80PCT, CGA_PLL1, PLL_DIV1 },
194 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
195 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
201 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
202 [1] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
211 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
212 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
213 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
227 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
228 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
229 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
251 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
252 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
253 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
260 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
261 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
262 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
263 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
278 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
279 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
286 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
287 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
288 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
289 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
304 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
305 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
313 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
314 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
335 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
336 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
337 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
352 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
359 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
360 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
361 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
362 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
377 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
378 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
384 [0] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
386 [2] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
393 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
394 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
395 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
401 [6] = { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
408 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
409 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
410 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
411 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
426 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
427 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
434 { CLKSEL_VALID, CGA_PLL1, PLL_DIV1 },
435 { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 },
436 { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 },
437 { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 },
569 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
587 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
600 BIT(CGA_PLL1) | BIT(CGA_PLL2),
615 BIT(CGA_PLL1) | BIT(CGA_PLL2),
631 BIT(CGA_PLL1) | BIT(CGA_PLL2),
647 BIT(CGA_PLL1) | BIT(CGA_PLL2),
662 BIT(CGA_PLL1) | BIT(CGA_PLL2),
673 .pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
684 BIT(CGA_PLL1) | BIT(CGA_PLL2) |
697 BIT(CGA_PLL1) | BIT(CGA_PLL2) |
712 BIT(CGA_PLL1) | BIT(CGA_PLL2),
725 BIT(CGA_PLL1) | BIT(CGA_PLL2),
738 BIT(CGA_PLL1) | BIT(CGA_PLL2) |
752 BIT(CGA_PLL1) | BIT(CGA_PLL2),
765 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3),
780 .pll_mask = BIT(PLATFORM_PLL) | BIT(CGA_PLL1),
794 BIT(CGA_PLL1) | BIT(CGA_PLL2),
811 BIT(CGA_PLL1) | BIT(CGA_PLL2),
828 BIT(CGA_PLL1) | BIT(CGA_PLL2) | BIT(CGA_PLL3) |
1234 case CGA_PLL1: in create_one_pll()
1383 legacy_pll_init(np, CGA_PLL1 + idx); in core_pll_init()