1 // SPDX-License-Identifier: GPL-2.0
5  * Clock driver for LS1028A Display output interfaces(LCD, DPHY).
8 #include <linux/clk-provider.h>
19 /* PLLDIG register offsets and bit masks */
70 	val = readl(data->regs + PLLDIG_REG_PLLFM);  in plldig_enable()
76 	writel(val, data->regs + PLLDIG_REG_PLLFM);  in plldig_enable()
86 	val = readl(data->regs + PLLDIG_REG_PLLFM);  in plldig_disable()
91 	writel(val, data->regs + PLLDIG_REG_PLLFM);  in plldig_disable()
98 	return readl(data->regs + PLLDIG_REG_PLLFM) &  in plldig_is_enabled()
108 	val = readl(data->regs + PLLDIG_REG_PLLDV);  in plldig_recalc_rate()
123 	return DIV_ROUND_UP(data->vco_freq, rfdphi1);  in plldig_recalc_rate()
143 	req->rate = clamp(req->rate, PHI1_MIN_FREQ, PHI1_MAX_FREQ);  in plldig_determine_rate()
144 	div = plldig_calc_target_div(data->vco_freq, req->rate);  in plldig_determine_rate()
145 	req->rate = DIV_ROUND_UP(data->vco_freq, div);  in plldig_determine_rate()
158 	rfdphi1 = plldig_calc_target_div(data->vco_freq, rate);  in plldig_set_rate()
161 	val = readl(data->regs + PLLDIG_REG_PLLDV);  in plldig_set_rate()
164 	writel(val, data->regs + PLLDIG_REG_PLLDV);  in plldig_set_rate()
170 	return readl_poll_timeout_atomic(data->regs + PLLDIG_REG_PLLSR, cond,  in plldig_set_rate()
194 		return -EINVAL;  in plldig_init()
198 	if (data->vco_freq) {  in plldig_init()
199 		mfd = data->vco_freq / parent_rate;  in plldig_init()
200 		lltmp = data->vco_freq % parent_rate;  in plldig_init()
206 		data->vco_freq = parent_rate * mfd;  in plldig_init()
210 	writel(val, data->regs + PLLDIG_REG_PLLDV);  in plldig_init()
216 		writel(val, data->regs + PLLDIG_REG_PLLFD);  in plldig_init()
225 	struct device *dev = &pdev->dev;  in plldig_clk_probe()
230 		return -ENOMEM;  in plldig_clk_probe()
232 	data->regs = devm_platform_ioremap_resource(pdev, 0);  in plldig_clk_probe()
233 	if (IS_ERR(data->regs))  in plldig_clk_probe()
234 		return PTR_ERR(data->regs);  in plldig_clk_probe()
236 	data->hw.init = CLK_HW_INIT_PARENTS_DATA("dpclk",  in plldig_clk_probe()
241 	ret = devm_clk_hw_register(dev, &data->hw);  in plldig_clk_probe()
244 						dev->of_node->name);  in plldig_clk_probe()
249 					  &data->hw);  in plldig_clk_probe()
259 	if (!of_property_read_u32(dev->of_node, "fsl,vco-hz",  in plldig_clk_probe()
260 				  &data->vco_freq)) {  in plldig_clk_probe()
261 		if (data->vco_freq < PLLDIG_MIN_VCO_FREQ ||  in plldig_clk_probe()
262 		    data->vco_freq > PLLDIG_MAX_VCO_FREQ)  in plldig_clk_probe()
263 			return -EINVAL;  in plldig_clk_probe()
266 	return plldig_init(&data->hw);  in plldig_clk_probe()
270 	{ .compatible = "fsl,ls1028a-plldig" },
277 		.name = "plldig-clock",
286 MODULE_DESCRIPTION("LS1028A Display output interface pixel clock driver");