Lines Matching +full:milbeaut +full:- +full:m10v +full:- +full:clk +full:- +full:ccu
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
17 #define CLKSEL(n) (((n) - 1) * 4 + M10V_CLKSEL1)
20 #define M10V_PLL1DIV2 "pll1-2"
22 #define M10V_PLL2DIV2 "pll2-2"
24 #define M10V_PLL6DIV2 "pll6-2"
25 #define M10V_PLL6DIV3 "pll6-3"
27 #define M10V_PLL7DIV2 "pll7-2"
28 #define M10V_PLL7DIV5 "pll7-5"
31 #define M10V_PLL10DIV2 "pll10-2"
34 #define M10V_SPI_PARENT0 "spi-parent0"
35 #define M10V_SPI_PARENT1 "spi-parent1"
36 #define M10V_SPI_PARENT2 "spi-parent2"
37 #define M10V_UHS1CLK2_PARENT0 "uhs1clk2-parent0"
38 #define M10V_UHS1CLK2_PARENT1 "uhs1clk2-parent1"
39 #define M10V_UHS1CLK2_PARENT2 "uhs1clk2-parent2"
40 #define M10V_UHS1CLK1_PARENT0 "uhs1clk1-parent0"
41 #define M10V_UHS1CLK1_PARENT1 "uhs1clk1-parent1"
42 #define M10V_NFCLK_PARENT0 "nfclk-parent0"
43 #define M10V_NFCLK_PARENT1 "nfclk-parent1"
44 #define M10V_NFCLK_PARENT2 "nfclk-parent2"
45 #define M10V_NFCLK_PARENT3 "nfclk-parent3"
46 #define M10V_NFCLK_PARENT4 "nfclk-parent4"
47 #define M10V_NFCLK_PARENT5 "nfclk-parent5"
216 {M10V_PLL1, NULL, 1, 40, -1},
217 {M10V_PLL2, NULL, 1, 30, -1},
218 {M10V_PLL6, NULL, 1, 35, -1},
219 {M10V_PLL7, NULL, 1, 40, -1},
220 {M10V_PLL9, NULL, 1, 33, -1},
221 {M10V_PLL10, NULL, 5, 108, -1},
222 {M10V_PLL10DIV2, M10V_PLL10, 2, 1, -1},
223 {M10V_PLL11, NULL, 2, 75, -1},
227 {"usb2", NULL, 2, 1, -1},
228 {"pcisuppclk", NULL, 20, 1, -1},
229 {M10V_PLL1DIV2, M10V_PLL1, 2, 1, -1},
230 {M10V_PLL2DIV2, M10V_PLL2, 2, 1, -1},
231 {M10V_PLL6DIV2, M10V_PLL6, 2, 1, -1},
232 {M10V_PLL6DIV3, M10V_PLL6, 3, 1, -1},
233 {M10V_PLL7DIV2, M10V_PLL7, 2, 1, -1},
234 {M10V_PLL7DIV5, M10V_PLL7, 5, 1, -1},
235 {"ca7wd", M10V_PLL2DIV2, 12, 1, -1},
236 {"pclkca7wd", M10V_PLL1DIV2, 16, 1, -1},
237 {M10V_SPI_PARENT0, M10V_PLL10DIV2, 2, 1, -1},
238 {M10V_SPI_PARENT1, M10V_PLL10DIV2, 4, 1, -1},
239 {M10V_SPI_PARENT2, M10V_PLL7DIV2, 8, 1, -1},
240 {M10V_UHS1CLK2_PARENT0, M10V_PLL7, 4, 1, -1},
241 {M10V_UHS1CLK2_PARENT1, M10V_PLL7, 8, 1, -1},
242 {M10V_UHS1CLK2_PARENT2, M10V_PLL7, 16, 1, -1},
243 {M10V_UHS1CLK1_PARENT0, M10V_PLL7, 8, 1, -1},
244 {M10V_UHS1CLK1_PARENT1, M10V_PLL7, 16, 1, -1},
245 {M10V_NFCLK_PARENT0, M10V_PLL7DIV2, 8, 1, -1},
246 {M10V_NFCLK_PARENT1, M10V_PLL7DIV2, 10, 1, -1},
247 {M10V_NFCLK_PARENT2, M10V_PLL7DIV2, 13, 1, -1},
248 {M10V_NFCLK_PARENT3, M10V_PLL7DIV2, 16, 1, -1},
249 {M10V_NFCLK_PARENT4, M10V_PLL7DIV2, 40, 1, -1},
250 {M10V_NFCLK_PARENT5, M10V_PLL7DIV5, 10, 1, -1},
256 {"mclk400", M10V_PLL1DIV2, CLKSEL(10), 7, 3, mclk400_table, 0, -1},
257 {"mclk200", M10V_PLL1DIV2, CLKSEL(10), 3, 4, mclk200_table, 0, -1},
258 {"aclk400", M10V_PLL1DIV2, CLKSEL(10), 0, 3, aclk400_table, 0, -1},
259 {"aclk300", M10V_PLL2DIV2, CLKSEL(12), 0, 2, aclk300_table, 0, -1},
261 {"aclkexs", M10V_PLL1DIV2, CLKSEL(9), 16, 4, aclkexs_table, 0, -1},
263 {"hclkbmh", M10V_PLL1DIV2, CLKSEL(9), 12, 4, hclkbmh_table, 0, -1},
265 {"uhs1clk0", M10V_PLL7, CLKSEL(1), 3, 5, uhs1clk0_table, 0, -1},
266 {"uhs2clk", M10V_PLL6DIV3, CLKSEL(1), 18, 4, uhs2clk_table, 0, -1},
275 CLKSEL(1), 8, 31, uhs1clk1_mux_table, 0, -1},
285 val = readl(mux->reg) >> mux->shift; in m10v_mux_get_parent()
286 val &= mux->mask; in m10v_mux_get_parent()
288 return clk_mux_val_to_index(hw, mux->table, mux->flags, val); in m10v_mux_get_parent()
294 u32 val = clk_mux_index_to_val(mux->table, mux->flags, index); in m10v_mux_set_parent()
297 u32 write_en = BIT(fls(mux->mask) - 1); in m10v_mux_set_parent()
299 if (mux->lock) in m10v_mux_set_parent()
300 spin_lock_irqsave(mux->lock, flags); in m10v_mux_set_parent()
302 __acquire(mux->lock); in m10v_mux_set_parent()
304 reg = readl(mux->reg); in m10v_mux_set_parent()
305 reg &= ~(mux->mask << mux->shift); in m10v_mux_set_parent()
307 val = (val | write_en) << mux->shift; in m10v_mux_set_parent()
309 writel(reg, mux->reg); in m10v_mux_set_parent()
311 if (mux->lock) in m10v_mux_set_parent()
312 spin_unlock_irqrestore(mux->lock, flags); in m10v_mux_set_parent()
314 __release(mux->lock); in m10v_mux_set_parent()
338 return ERR_PTR(-ENOMEM); in m10v_clk_hw_register_mux()
346 mux->reg = reg; in m10v_clk_hw_register_mux()
347 mux->shift = shift; in m10v_clk_hw_register_mux()
348 mux->mask = mask; in m10v_clk_hw_register_mux()
349 mux->flags = clk_mux_flags; in m10v_clk_hw_register_mux()
350 mux->lock = lock; in m10v_clk_hw_register_mux()
351 mux->table = table; in m10v_clk_hw_register_mux()
352 mux->hw.init = &init; in m10v_clk_hw_register_mux()
354 hw = &mux->hw; in m10v_clk_hw_register_mux()
382 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_recalc_rate()
383 val &= clk_div_mask(divider->width); in m10v_clk_divider_recalc_rate()
385 return divider_recalc_rate(hw, parent_rate, val, divider->table, in m10v_clk_divider_recalc_rate()
386 divider->flags, divider->width); in m10v_clk_divider_recalc_rate()
395 if (divider->flags & CLK_DIVIDER_READ_ONLY) { in m10v_clk_divider_round_rate()
398 val = readl(divider->reg) >> divider->shift; in m10v_clk_divider_round_rate()
399 val &= clk_div_mask(divider->width); in m10v_clk_divider_round_rate()
401 return divider_ro_round_rate(hw, rate, prate, divider->table, in m10v_clk_divider_round_rate()
402 divider->width, divider->flags, in m10v_clk_divider_round_rate()
406 return divider_round_rate(hw, rate, prate, divider->table, in m10v_clk_divider_round_rate()
407 divider->width, divider->flags); in m10v_clk_divider_round_rate()
417 u32 write_en = BIT(divider->width - 1); in m10v_clk_divider_set_rate()
419 value = divider_get_val(rate, parent_rate, divider->table, in m10v_clk_divider_set_rate()
420 divider->width, divider->flags); in m10v_clk_divider_set_rate()
424 if (divider->lock) in m10v_clk_divider_set_rate()
425 spin_lock_irqsave(divider->lock, flags); in m10v_clk_divider_set_rate()
427 __acquire(divider->lock); in m10v_clk_divider_set_rate()
429 val = readl(divider->reg); in m10v_clk_divider_set_rate()
430 val &= ~(clk_div_mask(divider->width) << divider->shift); in m10v_clk_divider_set_rate()
432 val |= ((u32)value | write_en) << divider->shift; in m10v_clk_divider_set_rate()
433 writel(val, divider->reg); in m10v_clk_divider_set_rate()
435 if (divider->write_valid_reg) { in m10v_clk_divider_set_rate()
436 writel(M10V_DCHREQ, divider->write_valid_reg); in m10v_clk_divider_set_rate()
437 if (readl_poll_timeout(divider->write_valid_reg, val, in m10v_clk_divider_set_rate()
443 if (divider->lock) in m10v_clk_divider_set_rate()
444 spin_unlock_irqrestore(divider->lock, flags); in m10v_clk_divider_set_rate()
446 __release(divider->lock); in m10v_clk_divider_set_rate()
470 return ERR_PTR(-ENOMEM); in m10v_clk_hw_register_divider()
478 div->reg = reg; in m10v_clk_hw_register_divider()
479 div->shift = shift; in m10v_clk_hw_register_divider()
480 div->width = width; in m10v_clk_hw_register_divider()
481 div->flags = clk_divider_flags; in m10v_clk_hw_register_divider()
482 div->lock = lock; in m10v_clk_hw_register_divider()
483 div->hw.init = &init; in m10v_clk_hw_register_divider()
484 div->table = table; in m10v_clk_hw_register_divider()
485 div->write_valid_reg = write_valid_reg; in m10v_clk_hw_register_divider()
488 hw = &div->hw; in m10v_clk_hw_register_divider()
509 if ((factors->offset == CLKSEL(9)) || (factors->offset == CLKSEL(10))) in m10v_reg_div_pre()
514 hw = m10v_clk_hw_register_divider(NULL, factors->name, in m10v_reg_div_pre()
515 factors->parent_name, in m10v_reg_div_pre()
517 base + factors->offset, in m10v_reg_div_pre()
518 factors->shift, in m10v_reg_div_pre()
519 factors->width, factors->div_flags, in m10v_reg_div_pre()
520 factors->table, in m10v_reg_div_pre()
523 if (factors->onecell_idx >= 0) in m10v_reg_div_pre()
524 clk_data->hws[factors->onecell_idx] = hw; in m10v_reg_div_pre()
532 const char *pn = factors->parent_name ? in m10v_reg_fixed_pre()
533 factors->parent_name : parent_name; in m10v_reg_fixed_pre()
535 hw = clk_hw_register_fixed_factor(NULL, factors->name, pn, 0, in m10v_reg_fixed_pre()
536 factors->mult, factors->div); in m10v_reg_fixed_pre()
538 if (factors->onecell_idx >= 0) in m10v_reg_fixed_pre()
539 clk_data->hws[factors->onecell_idx] = hw; in m10v_reg_fixed_pre()
548 hw = m10v_clk_hw_register_mux(NULL, factors->name, in m10v_reg_mux_pre()
549 factors->parent_names, in m10v_reg_mux_pre()
550 factors->num_parents, in m10v_reg_mux_pre()
552 base + factors->offset, factors->shift, in m10v_reg_mux_pre()
553 factors->mask, factors->mux_flags, in m10v_reg_mux_pre()
554 factors->table, &m10v_crglock); in m10v_reg_mux_pre()
556 if (factors->onecell_idx >= 0) in m10v_reg_mux_pre()
557 clk_data->hws[factors->onecell_idx] = hw; in m10v_reg_mux_pre()
563 struct device *dev = &pdev->dev; in m10v_clk_probe()
564 struct device_node *np = dev->of_node; in m10v_clk_probe()
587 if (IS_ERR(m10v_clk_data->hws[id])) in m10v_clk_probe()
588 return PTR_ERR(m10v_clk_data->hws[id]); in m10v_clk_probe()
595 { .compatible = "socionext,milbeaut-m10v-ccu", },
602 .name = "m10v-ccu",
621 m10v_clk_data->num = M10V_NUM_CLKS; in m10v_cc_init()
641 m10v_clk_data->hws[id] = ERR_PTR(-EPROBE_DEFER); in m10v_cc_init()
657 m10v_clk_data->hws[M10V_RCLK_ID] = hw; in m10v_cc_init()
660 CLK_OF_DECLARE_DRIVER(m10v_cc, "socionext,milbeaut-m10v-ccu", m10v_cc_init);