1 // SPDX-License-Identifier: GPL-2.0+
4  * Copyright (C) 2022-2023 Loongson Technology Corporation Limited
9 #include <linux/clk-provider.h>
13 #include <linux/io-64-nonatomic-lo-hi.h>
14 #include <dt-bindings/clock/loongson,ls2k-clk.h>
30 	/* Must be last --ends in a flexible-array member. */
216 	 * The hda clk divisor in the upper 32bits and the clk-prodiver
278 	return (val & GENMASK(shift + width - 1, shift)) >> shift;  in loongson2_rate_part()
285 	struct loongson2_clk_data *clk = to_loongson2_clk(hw);  in loongson2_pll_recalc_rate()  local
287 	val  = readq(clk->reg);  in loongson2_pll_recalc_rate()
288 	mult = loongson2_rate_part(val, clk->mult_shift, clk->mult_width);  in loongson2_pll_recalc_rate()
289 	div  = loongson2_rate_part(val, clk->div_shift,  clk->div_width);  in loongson2_pll_recalc_rate()
303 	struct loongson2_clk_data *clk = to_loongson2_clk(hw);  in loongson2_freqscale_recalc_rate()  local
305 	val  = readq(clk->reg);  in loongson2_freqscale_recalc_rate()
306 	scale = loongson2_rate_part(val, clk->div_shift, clk->div_width) + 1;  in loongson2_freqscale_recalc_rate()
308 	if (clk->bit_idx)  in loongson2_freqscale_recalc_rate()
309 		mode = val & BIT(clk->bit_idx - 1);  in loongson2_freqscale_recalc_rate()
326 	struct loongson2_clk_data *clk;  in loongson2_clk_register()  local
329 	clk = devm_kzalloc(clp->dev, sizeof(*clk), GFP_KERNEL);  in loongson2_clk_register()
330 	if (!clk)  in loongson2_clk_register()
331 		return ERR_PTR(-ENOMEM);  in loongson2_clk_register()
333 	init.name  = cld->name;  in loongson2_clk_register()
339 	clk->reg	= clp->base + cld->reg_offset;  in loongson2_clk_register()
340 	clk->div_shift	= cld->div_shift;  in loongson2_clk_register()
341 	clk->div_width	= cld->div_width;  in loongson2_clk_register()
342 	clk->mult_shift	= cld->mult_shift;  in loongson2_clk_register()
343 	clk->mult_width	= cld->mult_width;  in loongson2_clk_register()
344 	clk->bit_idx	= cld->bit_idx;  in loongson2_clk_register()
345 	clk->hw.init	= &init;  in loongson2_clk_register()
347 	hw = &clk->hw;  in loongson2_clk_register()
348 	ret = devm_clk_hw_register(clp->dev, hw);  in loongson2_clk_register()
350 		clk = ERR_PTR(ret);  in loongson2_clk_register()
359 	struct device *dev = &pdev->dev;  in loongson2_clk_probe()
366 		return -EINVAL;  in loongson2_clk_probe()
368 	refclk_name = of_clk_get_parent_name(dev->of_node, 0);  in loongson2_clk_probe()
373 	for (p = data; p->name; p++)  in loongson2_clk_probe()
374 		clks_num = max(clks_num, p->id + 1);  in loongson2_clk_probe()
379 		return -ENOMEM;  in loongson2_clk_probe()
381 	clp->base = devm_platform_ioremap_resource(pdev, 0);  in loongson2_clk_probe()
382 	if (IS_ERR(clp->base))  in loongson2_clk_probe()
383 		return PTR_ERR(clp->base);  in loongson2_clk_probe()
385 	spin_lock_init(&clp->clk_lock);  in loongson2_clk_probe()
386 	clp->clk_data.num = clks_num;  in loongson2_clk_probe()
387 	clp->dev = dev;  in loongson2_clk_probe()
390 	memset_p((void **)clp->clk_data.hws, ERR_PTR(-ENOENT), clks_num);  in loongson2_clk_probe()
394 		parent_name = p->parent_name ? p->parent_name : refclk_name;  in loongson2_clk_probe()
396 		switch (p->type) {  in loongson2_clk_probe()
406 			hw = devm_clk_hw_register_divider(dev, p->name,  in loongson2_clk_probe()
408 							  clp->base + p->reg_offset,  in loongson2_clk_probe()
409 							  p->div_shift, p->div_width,  in loongson2_clk_probe()
412 							  &clp->clk_lock);  in loongson2_clk_probe()
415 			hw = devm_clk_hw_register_gate(dev, p->name, parent_name,  in loongson2_clk_probe()
416 						       p->flags,  in loongson2_clk_probe()
417 						       clp->base + p->reg_offset,  in loongson2_clk_probe()
418 						       p->bit_idx, 0,  in loongson2_clk_probe()
419 						       &clp->clk_lock);  in loongson2_clk_probe()
422 			hw = devm_clk_hw_register_fixed_rate(dev, p->name, parent_name,  in loongson2_clk_probe()
423 							     0, p->fixed_rate);  in loongson2_clk_probe()
426 			return dev_err_probe(dev, -EINVAL, "Invalid clk type\n");  in loongson2_clk_probe()
431 					     "Register clk: %s, type: %u failed!\n",  in loongson2_clk_probe()
432 					     p->name, p->type);  in loongson2_clk_probe()
434 		clp->clk_data.hws[p->id] = hw;  in loongson2_clk_probe()
437 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &clp->clk_data);  in loongson2_clk_probe()
441 	{ .compatible = "loongson,ls2k0300-clk", .data = &ls2k0300_clks },
442 	{ .compatible = "loongson,ls2k0500-clk", .data = &ls2k0500_clks },
443 	{ .compatible = "loongson,ls2k-clk", .data = &ls2k1000_clks },
444 	{ .compatible = "loongson,ls2k2000-clk", .data = &ls2k2000_clks },
452 		.name	= "loongson2-clk",