Lines Matching +full:spi +full:- +full:lsb +full:- +full:first
1 // SPDX-License-Identifier: GPL-2.0
3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
14 #include <linux/clk-provider.h>
20 #include <linux/spi/spi.h>
22 /* 0x000 - 0x00d System Functions */
34 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
75 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
124 /* 0x146 - 0x14a CLKin Control */
134 /* 0x14b - 0x152 Holdover */
136 /* 0x153 - 0x15f PLL1 Configuration */
143 /* 0x160 - 0x16e PLL2 Configuration */
166 /* 0x16F - 0x555 Misc Registers */
183 * struct lmk04832_device_info - Holds static device information that is
232 * struct lmk04832 - The LMK04832 device structure
334 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp); in lmk04832_vco_is_enabled()
348 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD, in lmk04832_vco_prepare()
355 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_vco_prepare()
365 regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD, in lmk04832_vco_unprepare()
370 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_vco_unprepare()
385 ret = regmap_read(lmk->regmap, LMK04832_REG_PLL2_MISC, &pll2_misc); in lmk04832_vco_recalc_rate()
391 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_N_0, &tmp, 3); in lmk04832_vco_recalc_rate()
399 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_R_MSB, &tmp, 2); in lmk04832_vco_recalc_rate()
413 * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges
425 struct spi_device *spi = to_spi_device(lmk->dev); in lmk04832_check_vco_ranges() local
429 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data]; in lmk04832_check_vco_ranges()
431 if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1]) in lmk04832_check_vco_ranges()
434 if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1]) in lmk04832_check_vco_ranges()
437 dev_err(lmk->dev, "%lu Hz is out of VCO ranges\n", rate); in lmk04832_check_vco_ranges()
438 return -ERANGE; in lmk04832_check_vco_ranges()
442 * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency
483 return -EINVAL; in lmk04832_calc_pll2_params()
485 return -EINVAL; in lmk04832_calc_pll2_params()
502 ret = lmk04832_check_vco_ranges(lmk, req->rate); in lmk04832_vco_determine_rate()
506 vco_rate = lmk04832_calc_pll2_params(req->best_parent_rate, req->rate, in lmk04832_vco_determine_rate()
509 dev_err(lmk->dev, "PLL2 parameters out of range\n"); in lmk04832_vco_determine_rate()
510 req->rate = vco_rate; in lmk04832_vco_determine_rate()
515 if (req->rate != vco_rate) in lmk04832_vco_determine_rate()
516 return -EINVAL; in lmk04832_vco_determine_rate()
518 req->rate = vco_rate; in lmk04832_vco_determine_rate()
536 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT, in lmk04832_vco_set_rate()
544 dev_err(lmk->dev, "failed to determine PLL2 parameters\n"); in lmk04832_vco_set_rate()
548 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_R_MSB, in lmk04832_vco_set_rate()
554 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_R_LSB, in lmk04832_vco_set_rate()
559 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC, in lmk04832_vco_set_rate()
569 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0, in lmk04832_vco_set_rate()
573 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_1, in lmk04832_vco_set_rate()
578 return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2, in lmk04832_vco_set_rate()
592 * lmk04832_register_vco - Initialize the internal VCO and clock distribution
601 init.name = "lmk-vco"; in lmk04832_register_vco()
602 parent_names[0] = __clk_get_name(lmk->oscin); in lmk04832_register_vco()
608 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT, in lmk04832_register_vco()
615 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_FB_CTRL, in lmk04832_register_vco()
625 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC, in lmk04832_register_vco()
631 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_LD, in lmk04832_register_vco()
639 lmk->vco.init = &init; in lmk04832_register_vco()
640 return devm_clk_hw_register(lmk->dev, &lmk->vco); in lmk04832_register_vco()
645 static const int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0}; in lmk04832_clkout_set_ddly()
651 unsigned int lsb, msb; in lmk04832_clkout_set_ddly() local
654 ret = regmap_update_bits(lmk->regmap, in lmk04832_clkout_set_ddly()
661 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb); in lmk04832_clkout_set_ddly()
665 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb); in lmk04832_clkout_set_ddly()
669 sysref_ddly = FIELD_GET(LMK04832_BIT_SYSREF_DDLY_MSB, msb) << 8 | lsb; in lmk04832_clkout_set_ddly()
671 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb); in lmk04832_clkout_set_ddly()
675 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb); in lmk04832_clkout_set_ddly()
679 dclkx_y_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb; in lmk04832_clkout_set_ddly()
681 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb); in lmk04832_clkout_set_ddly()
685 dclkx_y_hs = FIELD_GET(LMK04832_BIT_DCLKX_Y_HS, lsb); in lmk04832_clkout_set_ddly()
687 dclkx_y_ddly = sysref_ddly + 1 - in lmk04832_clkout_set_ddly()
688 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7] - in lmk04832_clkout_set_ddly()
692 dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n", in lmk04832_clkout_set_ddly()
694 return -EINVAL; in lmk04832_clkout_set_ddly()
697 ret = regmap_write(lmk->regmap, in lmk04832_clkout_set_ddly()
703 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id), in lmk04832_clkout_set_ddly()
708 dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, " in lmk04832_clkout_set_ddly()
714 return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), in lmk04832_clkout_set_ddly()
719 /** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk
725 * - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31
727 * - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972
738 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_sclk_sync_sequence()
744 for (i = 0; i < lmk->clk_data->num; i += 2) { in lmk04832_sclk_sync_sequence()
754 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, in lmk04832_sclk_sync_sequence()
763 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
771 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00); in lmk04832_sclk_sync_sequence()
778 * PLL2-only use case, this will be complete in less than one SPI in lmk04832_sclk_sync_sequence()
782 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
788 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
800 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
806 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
813 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff); in lmk04832_sclk_sync_sequence()
818 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, in lmk04832_sclk_sync_sequence()
821 lmk->sysref_mux)); in lmk04832_sclk_sync_sequence()
825 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
828 lmk->sync_mode)); in lmk04832_sclk_sync_sequence()
855 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp); in lmk04832_sclk_is_enabled()
866 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_sclk_prepare()
874 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_sclk_unprepare()
886 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, &tmp, 2); in lmk04832_sclk_recalc_rate()
903 sysref_div = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate); in lmk04832_sclk_determine_rate()
904 sclk_rate = DIV_ROUND_CLOSEST(req->best_parent_rate, sysref_div); in lmk04832_sclk_determine_rate()
907 dev_err(lmk->dev, "SYSREF divider out of range\n"); in lmk04832_sclk_determine_rate()
908 return -EINVAL; in lmk04832_sclk_determine_rate()
911 if (req->rate != sclk_rate) in lmk04832_sclk_determine_rate()
912 return -EINVAL; in lmk04832_sclk_determine_rate()
914 req->rate = sclk_rate; in lmk04832_sclk_determine_rate()
929 dev_err(lmk->dev, "SYSREF divider out of range\n"); in lmk04832_sclk_set_rate()
930 return -EINVAL; in lmk04832_sclk_set_rate()
933 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, in lmk04832_sclk_set_rate()
938 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB, in lmk04832_sclk_set_rate()
945 dev_err(lmk->dev, "SYNC sequence failed\n"); in lmk04832_sclk_set_rate()
965 init.name = "lmk-sclk"; in lmk04832_register_sclk()
966 parent_names[0] = clk_hw_get_name(&lmk->vco); in lmk04832_register_sclk()
973 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, in lmk04832_register_sclk()
976 lmk->sysref_mux)); in lmk04832_register_sclk()
980 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, in lmk04832_register_sclk()
981 FIELD_GET(0x00ff, lmk->sysref_ddly)); in lmk04832_register_sclk()
985 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, in lmk04832_register_sclk()
986 FIELD_GET(0x1f00, lmk->sysref_ddly)); in lmk04832_register_sclk()
990 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT, in lmk04832_register_sclk()
991 ilog2(lmk->sysref_pulse_cnt)); in lmk04832_register_sclk()
995 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_register_sclk()
1003 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_register_sclk()
1006 FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode)); in lmk04832_register_sclk()
1010 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff); in lmk04832_register_sclk()
1014 lmk->sclk.init = &init; in lmk04832_register_sclk()
1015 return devm_clk_hw_register(lmk->dev, &lmk->sclk); in lmk04832_register_sclk()
1021 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_is_enabled()
1025 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_is_enabled()
1036 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_prepare()
1038 return regmap_update_bits(lmk->regmap, in lmk04832_dclk_prepare()
1039 LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_prepare()
1046 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_unprepare()
1048 regmap_update_bits(lmk->regmap, in lmk04832_dclk_unprepare()
1049 LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_unprepare()
1057 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_recalc_rate()
1059 unsigned int lsb, msb; in lmk04832_dclk_recalc_rate() local
1063 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id), in lmk04832_dclk_recalc_rate()
1064 &lsb); in lmk04832_dclk_recalc_rate()
1068 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(dclk->id), in lmk04832_dclk_recalc_rate()
1073 dclk_div = FIELD_GET(LMK04832_BIT_DCLK_DIV_MSB, msb) << 8 | lsb; in lmk04832_dclk_recalc_rate()
1083 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_determine_rate()
1087 dclk_div = DIV_ROUND_CLOSEST(req->best_parent_rate, req->rate); in lmk04832_dclk_determine_rate()
1088 dclk_rate = DIV_ROUND_CLOSEST(req->best_parent_rate, dclk_div); in lmk04832_dclk_determine_rate()
1091 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw)); in lmk04832_dclk_determine_rate()
1092 return -EINVAL; in lmk04832_dclk_determine_rate()
1095 if (req->rate != dclk_rate) in lmk04832_dclk_determine_rate()
1096 return -EINVAL; in lmk04832_dclk_determine_rate()
1098 req->rate = dclk_rate; in lmk04832_dclk_determine_rate()
1107 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_set_rate()
1114 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw)); in lmk04832_dclk_set_rate()
1115 return -EINVAL; in lmk04832_dclk_set_rate()
1120 ret = regmap_update_bits(lmk->regmap, in lmk04832_dclk_set_rate()
1121 LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_set_rate()
1129 * While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC in lmk04832_dclk_set_rate()
1130 * procedure requires to first program Divide-by-4 and then back to in lmk04832_dclk_set_rate()
1131 * Divide-by-2 or Divide-by-3 before doing SYNC. in lmk04832_dclk_set_rate()
1134 ret = regmap_update_bits(lmk->regmap, in lmk04832_dclk_set_rate()
1135 LMK04832_REG_CLKOUT_CTRL2(dclk->id), in lmk04832_dclk_set_rate()
1140 ret = regmap_write(lmk->regmap, in lmk04832_dclk_set_rate()
1141 LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04); in lmk04832_dclk_set_rate()
1146 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id), in lmk04832_dclk_set_rate()
1151 ret = regmap_update_bits(lmk->regmap, in lmk04832_dclk_set_rate()
1152 LMK04832_REG_CLKOUT_CTRL2(dclk->id), in lmk04832_dclk_set_rate()
1160 dev_err(lmk->dev, "SYNC sequence failed\n"); in lmk04832_dclk_set_rate()
1177 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_is_enabled()
1185 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(clkout->id), in lmk04832_clkout_is_enabled()
1192 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), in lmk04832_clkout_is_enabled()
1198 ret = regmap_read(lmk->regmap, in lmk04832_clkout_is_enabled()
1199 LMK04832_REG_CLKOUT_CTRL4(clkout->id), in lmk04832_clkout_is_enabled()
1207 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id), in lmk04832_clkout_is_enabled()
1212 if (clkout->id % 2) in lmk04832_clkout_is_enabled()
1223 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_prepare()
1227 if (clkout->format == LMK04832_VAL_CLKOUT_FMT_POWERDOWN) in lmk04832_clkout_prepare()
1228 dev_err(lmk->dev, "prepared %s but format is powerdown\n", in lmk04832_clkout_prepare()
1231 ret = regmap_update_bits(lmk->regmap, in lmk04832_clkout_prepare()
1232 LMK04832_REG_CLKOUT_CTRL2(clkout->id), in lmk04832_clkout_prepare()
1237 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), in lmk04832_clkout_prepare()
1243 ret = regmap_update_bits(lmk->regmap, in lmk04832_clkout_prepare()
1244 LMK04832_REG_CLKOUT_CTRL4(clkout->id), in lmk04832_clkout_prepare()
1250 return regmap_update_bits(lmk->regmap, in lmk04832_clkout_prepare()
1251 LMK04832_REG_CLKOUT_FMT(clkout->id), in lmk04832_clkout_prepare()
1252 LMK04832_BIT_CLKOUT_FMT(clkout->id), in lmk04832_clkout_prepare()
1253 clkout->format << 4 * (clkout->id % 2)); in lmk04832_clkout_prepare()
1259 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_unprepare()
1261 regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id), in lmk04832_clkout_unprepare()
1262 LMK04832_BIT_CLKOUT_FMT(clkout->id), in lmk04832_clkout_unprepare()
1269 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_set_parent()
1271 return regmap_update_bits(lmk->regmap, in lmk04832_clkout_set_parent()
1272 LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), in lmk04832_clkout_set_parent()
1281 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_get_parent()
1285 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), in lmk04832_clkout_get_parent()
1304 char name[] = "lmk-clkoutXX"; in lmk04832_register_clkout()
1305 char dclk_name[] = "lmk-dclkXX_YY"; in lmk04832_register_clkout()
1312 sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1); in lmk04832_register_clkout()
1314 parent_names[0] = clk_hw_get_name(&lmk->vco); in lmk04832_register_clkout()
1320 lmk->dclk[dclk_num].id = num; in lmk04832_register_clkout()
1321 lmk->dclk[dclk_num].lmk = lmk; in lmk04832_register_clkout()
1322 lmk->dclk[dclk_num].hw.init = &init; in lmk04832_register_clkout()
1324 ret = devm_clk_hw_register(lmk->dev, &lmk->dclk[dclk_num].hw); in lmk04832_register_clkout()
1328 sprintf(dclk_name, "lmk-dclk%02d_%02d", num - 1, num); in lmk04832_register_clkout()
1331 if (of_property_read_string_index(lmk->dev->of_node, in lmk04832_register_clkout()
1332 "clock-output-names", in lmk04832_register_clkout()
1334 sprintf(name, "lmk-clkout%02d", num); in lmk04832_register_clkout()
1339 parent_names[1] = clk_hw_get_name(&lmk->sclk); in lmk04832_register_clkout()
1345 lmk->clkout[num].id = num; in lmk04832_register_clkout()
1346 lmk->clkout[num].lmk = lmk; in lmk04832_register_clkout()
1347 lmk->clkout[num].hw.init = &init; in lmk04832_register_clkout()
1348 lmk->clk_data->hws[num] = &lmk->clkout[num].hw; in lmk04832_register_clkout()
1351 regmap_update_bits(lmk->regmap, in lmk04832_register_clkout()
1355 lmk->clkout[num].sysref)); in lmk04832_register_clkout()
1357 return devm_clk_hw_register(lmk->dev, &lmk->clkout[num].hw); in lmk04832_register_clkout()
1369 dev_info(lmk->dev, "setting up 4-wire mode\n"); in lmk04832_set_spi_rdbk()
1370 ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W, in lmk04832_set_spi_rdbk()
1393 return -EINVAL; in lmk04832_set_spi_rdbk()
1396 return regmap_write(lmk->regmap, reg, val); in lmk04832_set_spi_rdbk()
1399 static int lmk04832_probe(struct spi_device *spi) in lmk04832_probe() argument
1409 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data]; in lmk04832_probe()
1411 lmk = devm_kzalloc(&spi->dev, sizeof(struct lmk04832), GFP_KERNEL); in lmk04832_probe()
1413 return -ENOMEM; in lmk04832_probe()
1415 lmk->dev = &spi->dev; in lmk04832_probe()
1417 lmk->oscin = devm_clk_get_enabled(lmk->dev, "oscin"); in lmk04832_probe()
1418 if (IS_ERR(lmk->oscin)) { in lmk04832_probe()
1419 dev_err(lmk->dev, "failed to get oscin clock\n"); in lmk04832_probe()
1420 return PTR_ERR(lmk->oscin); in lmk04832_probe()
1423 lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", in lmk04832_probe()
1426 lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1, in lmk04832_probe()
1428 if (!lmk->dclk) { in lmk04832_probe()
1429 ret = -ENOMEM; in lmk04832_probe()
1433 lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels, in lmk04832_probe()
1434 sizeof(*lmk->clkout), GFP_KERNEL); in lmk04832_probe()
1435 if (!lmk->clkout) { in lmk04832_probe()
1436 ret = -ENOMEM; in lmk04832_probe()
1440 lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws, in lmk04832_probe()
1441 info->num_channels), in lmk04832_probe()
1443 if (!lmk->clk_data) { in lmk04832_probe()
1444 ret = -ENOMEM; in lmk04832_probe()
1448 device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate); in lmk04832_probe()
1450 lmk->sysref_ddly = 8; in lmk04832_probe()
1451 device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly); in lmk04832_probe()
1453 lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS; in lmk04832_probe()
1454 device_property_read_u32(lmk->dev, "ti,sysref-mux", in lmk04832_probe()
1455 &lmk->sysref_mux); in lmk04832_probe()
1457 lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF; in lmk04832_probe()
1458 device_property_read_u32(lmk->dev, "ti,sync-mode", in lmk04832_probe()
1459 &lmk->sync_mode); in lmk04832_probe()
1461 lmk->sysref_pulse_cnt = 4; in lmk04832_probe()
1462 device_property_read_u32(lmk->dev, "ti,sysref-pulse-count", in lmk04832_probe()
1463 &lmk->sysref_pulse_cnt); in lmk04832_probe()
1465 for_each_child_of_node(lmk->dev->of_node, child) { in lmk04832_probe()
1470 dev_err(lmk->dev, "missing reg property in child: %s\n", in lmk04832_probe()
1471 child->full_name); in lmk04832_probe()
1476 of_property_read_u32(child, "ti,clkout-fmt", in lmk04832_probe()
1477 &lmk->clkout[reg].format); in lmk04832_probe()
1479 if (lmk->clkout[reg].format >= 0x0a && reg % 2 == 0 in lmk04832_probe()
1481 dev_err(lmk->dev, "invalid format for clkout%02d\n", in lmk04832_probe()
1484 lmk->clkout[reg].sysref = in lmk04832_probe()
1485 of_property_read_bool(child, "ti,clkout-sysref"); in lmk04832_probe()
1488 lmk->regmap = devm_regmap_init_spi(spi, ®map_config); in lmk04832_probe()
1489 if (IS_ERR(lmk->regmap)) { in lmk04832_probe()
1490 dev_err(lmk->dev, "%s: regmap allocation failed: %ld\n", in lmk04832_probe()
1492 __func__, PTR_ERR(lmk->regmap)); in lmk04832_probe()
1493 ret = PTR_ERR(lmk->regmap); in lmk04832_probe()
1497 regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET); in lmk04832_probe()
1499 if (!(spi->mode & SPI_3WIRE)) { in lmk04832_probe()
1500 device_property_read_u32(lmk->dev, "ti,spi-4wire-rdbk", in lmk04832_probe()
1507 regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3); in lmk04832_probe()
1508 if ((tmp[0] << 8 | tmp[1]) != info->pid || tmp[2] != info->maskrev) { in lmk04832_probe()
1509 dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n", in lmk04832_probe()
1511 ret = -EINVAL; in lmk04832_probe()
1517 dev_err(lmk->dev, "failed to init device clock path\n"); in lmk04832_probe()
1521 if (lmk->vco_rate) { in lmk04832_probe()
1522 dev_info(lmk->dev, "setting VCO rate to %u Hz\n", lmk->vco_rate); in lmk04832_probe()
1523 ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate); in lmk04832_probe()
1525 dev_err(lmk->dev, "failed to set VCO rate\n"); in lmk04832_probe()
1532 dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n"); in lmk04832_probe()
1536 for (i = 0; i < info->num_channels; i++) { in lmk04832_probe()
1539 dev_err(lmk->dev, "failed to register clk %d\n", i); in lmk04832_probe()
1544 lmk->clk_data->num = info->num_channels; in lmk04832_probe()
1545 ret = devm_of_clk_add_hw_provider(lmk->dev, of_clk_hw_onecell_get, in lmk04832_probe()
1546 lmk->clk_data); in lmk04832_probe()
1548 dev_err(lmk->dev, "failed to add provider (%d)\n", ret); in lmk04832_probe()
1552 spi_set_drvdata(spi, lmk); in lmk04832_probe()
1561 MODULE_DEVICE_TABLE(spi, lmk04832_id);