Lines Matching +full:clkout +full:- +full:clock
1 // SPDX-License-Identifier: GPL-2.0
3 * LMK04832 Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner
14 #include <linux/clk-provider.h>
22 /* 0x000 - 0x00d System Functions */
34 /* 0x100 - 0x137 Device Clock and SYSREF Clock Output Control */
75 /* 0x138 - 0x145 SYSREF, SYNC, and Device Config */
124 /* 0x146 - 0x14a CLKin Control */
134 /* 0x14b - 0x152 Holdover */
136 /* 0x153 - 0x15f PLL1 Configuration */
143 /* 0x160 - 0x16e PLL2 Configuration */
166 /* 0x16F - 0x555 Misc Registers */
183 * struct lmk04832_device_info - Holds static device information that is
188 * @num_channels: Number of available output channels (clkout count)
232 * struct lmk04832 - The LMK04832 device structure
241 * @oscin: PLL2 input clock
242 * @vco: reference to the internal VCO clock
243 * @sclk: reference to the internal sysref clock (SCLK)
246 * @dclk: list of internal device clock references.
247 * Each pair of clkout clocks share a single device clock (DCLKX_Y)
248 * @clkout: list of output clock references
249 * @clk_data: holds clkout related data like clk_hw* and number of clocks
268 struct lmk_clkout *clkout; member
334 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp); in lmk04832_vco_is_enabled()
348 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD, in lmk04832_vco_prepare()
355 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_vco_prepare()
365 regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_PD, in lmk04832_vco_unprepare()
370 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_vco_unprepare()
385 ret = regmap_read(lmk->regmap, LMK04832_REG_PLL2_MISC, &pll2_misc); in lmk04832_vco_recalc_rate()
391 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_N_0, &tmp, 3); in lmk04832_vco_recalc_rate()
399 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_PLL2_R_MSB, &tmp, 2); in lmk04832_vco_recalc_rate()
413 * lmk04832_check_vco_ranges - Check requested VCO frequency against VCO ranges
425 struct spi_device *spi = to_spi_device(lmk->dev); in lmk04832_check_vco_ranges()
429 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data]; in lmk04832_check_vco_ranges()
431 if (mhz >= info->vco0_range[0] && mhz <= info->vco0_range[1]) in lmk04832_check_vco_ranges()
434 if (mhz >= info->vco1_range[0] && mhz <= info->vco1_range[1]) in lmk04832_check_vco_ranges()
437 dev_err(lmk->dev, "%lu Hz is out of VCO ranges\n", rate); in lmk04832_check_vco_ranges()
438 return -ERANGE; in lmk04832_check_vco_ranges()
442 * lmk04832_calc_pll2_params - Get PLL2 parameters used to set the VCO frequency
483 return -EINVAL; in lmk04832_calc_pll2_params()
485 return -EINVAL; in lmk04832_calc_pll2_params()
508 dev_err(lmk->dev, "PLL2 parameters out of range\n"); in lmk04832_vco_round_rate()
513 return -EINVAL; in lmk04832_vco_round_rate()
531 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT, in lmk04832_vco_set_rate()
539 dev_err(lmk->dev, "failed to determine PLL2 parameters\n"); in lmk04832_vco_set_rate()
543 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_R_MSB, in lmk04832_vco_set_rate()
549 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_R_LSB, in lmk04832_vco_set_rate()
554 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC, in lmk04832_vco_set_rate()
564 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_0, in lmk04832_vco_set_rate()
568 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_1, in lmk04832_vco_set_rate()
573 return regmap_write(lmk->regmap, LMK04832_REG_PLL2_N_2, in lmk04832_vco_set_rate()
587 * lmk04832_register_vco - Initialize the internal VCO and clock distribution
596 init.name = "lmk-vco"; in lmk04832_register_vco()
597 parent_names[0] = __clk_get_name(lmk->oscin); in lmk04832_register_vco()
603 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_VCO_OSCOUT, in lmk04832_register_vco()
610 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_FB_CTRL, in lmk04832_register_vco()
620 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_PLL2_MISC, in lmk04832_register_vco()
626 ret = regmap_write(lmk->regmap, LMK04832_REG_PLL2_LD, in lmk04832_register_vco()
634 lmk->vco.init = &init; in lmk04832_register_vco()
635 return devm_clk_hw_register(lmk->dev, &lmk->vco); in lmk04832_register_vco()
640 const int dclk_div_adj[] = {0, 0, -2, -2, 0, 3, -1, 0}; in lmk04832_clkout_set_ddly()
649 ret = regmap_update_bits(lmk->regmap, in lmk04832_clkout_set_ddly()
656 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, &lsb); in lmk04832_clkout_set_ddly()
660 ret = regmap_read(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, &msb); in lmk04832_clkout_set_ddly()
666 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(id), &lsb); in lmk04832_clkout_set_ddly()
670 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), &msb); in lmk04832_clkout_set_ddly()
676 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(id), &lsb); in lmk04832_clkout_set_ddly()
682 dclkx_y_ddly = sysref_ddly + 1 - in lmk04832_clkout_set_ddly()
683 dclk_div_adj[dclkx_y_div < 6 ? dclkx_y_div : 7] - in lmk04832_clkout_set_ddly()
687 dev_err(lmk->dev, "DCLKX_Y_DDLY out of range (%d)\n", in lmk04832_clkout_set_ddly()
689 return -EINVAL; in lmk04832_clkout_set_ddly()
692 ret = regmap_write(lmk->regmap, in lmk04832_clkout_set_ddly()
698 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL1(id), in lmk04832_clkout_set_ddly()
703 dev_dbg(lmk->dev, "clkout%02u: sysref_ddly=%u, dclkx_y_ddly=%u, " in lmk04832_clkout_set_ddly()
709 return regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(id), in lmk04832_clkout_set_ddly()
714 /** lmk04832_sclk_sync - Establish deterministic phase relationship between sclk
720 * - in the datasheet https://www.ti.com/lit/ds/symlink/lmk04832.pdf, p.31
722 * - Ti forum: https://e2e.ti.com/support/clock-and-timing/f/48/t/970972
732 /* 2. Enable and write device clock digital delay to applicable clocks */ in lmk04832_sclk_sync_sequence()
733 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_sclk_sync_sequence()
739 for (i = 0; i < lmk->clk_data->num; i += 2) { in lmk04832_sclk_sync_sequence()
749 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, in lmk04832_sclk_sync_sequence()
758 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
766 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0x00); in lmk04832_sclk_sync_sequence()
771 * 5. If SCLKX_Y_DDLY != 0, Set SYSREF_CLR=1 for at least 15 clock in lmk04832_sclk_sync_sequence()
773 * PLL2-only use case, this will be complete in less than one SPI in lmk04832_sclk_sync_sequence()
777 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
783 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
795 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
801 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
808 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff); in lmk04832_sclk_sync_sequence()
813 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, in lmk04832_sclk_sync_sequence()
816 lmk->sysref_mux)); in lmk04832_sclk_sync_sequence()
820 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_sclk_sync_sequence()
823 lmk->sync_mode)); in lmk04832_sclk_sync_sequence()
850 ret = regmap_read(lmk->regmap, LMK04832_REG_MAIN_PD, &tmp); in lmk04832_sclk_is_enabled()
861 return regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_sclk_prepare()
869 regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_sclk_unprepare()
881 ret = regmap_bulk_read(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, &tmp, 2); in lmk04832_sclk_recalc_rate()
902 dev_err(lmk->dev, "SYSREF divider out of range\n"); in lmk04832_sclk_round_rate()
903 return -EINVAL; in lmk04832_sclk_round_rate()
907 return -EINVAL; in lmk04832_sclk_round_rate()
922 dev_err(lmk->dev, "SYSREF divider out of range\n"); in lmk04832_sclk_set_rate()
923 return -EINVAL; in lmk04832_sclk_set_rate()
926 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_MSB, in lmk04832_sclk_set_rate()
931 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DIV_LSB, in lmk04832_sclk_set_rate()
938 dev_err(lmk->dev, "SYNC sequence failed\n"); in lmk04832_sclk_set_rate()
958 init.name = "lmk-sclk"; in lmk04832_register_sclk()
959 parent_names[0] = clk_hw_get_name(&lmk->vco); in lmk04832_register_sclk()
966 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_SYSREF_OUT, in lmk04832_register_sclk()
969 lmk->sysref_mux)); in lmk04832_register_sclk()
973 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_LSB, in lmk04832_register_sclk()
974 FIELD_GET(0x00ff, lmk->sysref_ddly)); in lmk04832_register_sclk()
978 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_DDLY_MSB, in lmk04832_register_sclk()
979 FIELD_GET(0x1f00, lmk->sysref_ddly)); in lmk04832_register_sclk()
983 ret = regmap_write(lmk->regmap, LMK04832_REG_SYSREF_PULSE_CNT, in lmk04832_register_sclk()
984 ilog2(lmk->sysref_pulse_cnt)); in lmk04832_register_sclk()
988 ret = regmap_update_bits(lmk->regmap, LMK04832_REG_MAIN_PD, in lmk04832_register_sclk()
996 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC, in lmk04832_register_sclk()
999 FIELD_PREP(LMK04832_BIT_SYNC_MODE, lmk->sync_mode)); in lmk04832_register_sclk()
1003 ret = regmap_write(lmk->regmap, LMK04832_REG_SYNC_DIS, 0xff); in lmk04832_register_sclk()
1007 lmk->sclk.init = &init; in lmk04832_register_sclk()
1008 return devm_clk_hw_register(lmk->dev, &lmk->sclk); in lmk04832_register_sclk()
1014 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_is_enabled()
1018 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_is_enabled()
1029 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_prepare()
1031 return regmap_update_bits(lmk->regmap, in lmk04832_dclk_prepare()
1032 LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_prepare()
1039 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_unprepare()
1041 regmap_update_bits(lmk->regmap, in lmk04832_dclk_unprepare()
1042 LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_unprepare()
1050 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_recalc_rate()
1056 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id), in lmk04832_dclk_recalc_rate()
1061 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(dclk->id), in lmk04832_dclk_recalc_rate()
1076 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_round_rate()
1084 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw)); in lmk04832_dclk_round_rate()
1085 return -EINVAL; in lmk04832_dclk_round_rate()
1089 return -EINVAL; in lmk04832_dclk_round_rate()
1098 struct lmk04832 *lmk = dclk->lmk; in lmk04832_dclk_set_rate()
1105 dev_err(lmk->dev, "%s_div out of range\n", clk_hw_get_name(hw)); in lmk04832_dclk_set_rate()
1106 return -EINVAL; in lmk04832_dclk_set_rate()
1111 ret = regmap_update_bits(lmk->regmap, in lmk04832_dclk_set_rate()
1112 LMK04832_REG_CLKOUT_CTRL3(dclk->id), in lmk04832_dclk_set_rate()
1120 * While using Divide-by-2 or Divide-by-3 for DCLK_X_Y_DIV, SYNC in lmk04832_dclk_set_rate()
1121 * procedure requires to first program Divide-by-4 and then back to in lmk04832_dclk_set_rate()
1122 * Divide-by-2 or Divide-by-3 before doing SYNC. in lmk04832_dclk_set_rate()
1125 ret = regmap_update_bits(lmk->regmap, in lmk04832_dclk_set_rate()
1126 LMK04832_REG_CLKOUT_CTRL2(dclk->id), in lmk04832_dclk_set_rate()
1131 ret = regmap_write(lmk->regmap, in lmk04832_dclk_set_rate()
1132 LMK04832_REG_CLKOUT_CTRL0(dclk->id), 0x04); in lmk04832_dclk_set_rate()
1137 ret = regmap_write(lmk->regmap, LMK04832_REG_CLKOUT_CTRL0(dclk->id), in lmk04832_dclk_set_rate()
1142 ret = regmap_update_bits(lmk->regmap, in lmk04832_dclk_set_rate()
1143 LMK04832_REG_CLKOUT_CTRL2(dclk->id), in lmk04832_dclk_set_rate()
1151 dev_err(lmk->dev, "SYNC sequence failed\n"); in lmk04832_dclk_set_rate()
1167 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); in lmk04832_clkout_is_enabled() local
1168 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_is_enabled()
1176 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_CTRL2(clkout->id), in lmk04832_clkout_is_enabled()
1183 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), in lmk04832_clkout_is_enabled()
1189 ret = regmap_read(lmk->regmap, in lmk04832_clkout_is_enabled()
1190 LMK04832_REG_CLKOUT_CTRL4(clkout->id), in lmk04832_clkout_is_enabled()
1198 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id), in lmk04832_clkout_is_enabled()
1203 if (clkout->id % 2) in lmk04832_clkout_is_enabled()
1213 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); in lmk04832_clkout_prepare() local
1214 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_prepare()
1218 if (clkout->format == LMK04832_VAL_CLKOUT_FMT_POWERDOWN) in lmk04832_clkout_prepare()
1219 dev_err(lmk->dev, "prepared %s but format is powerdown\n", in lmk04832_clkout_prepare()
1222 ret = regmap_update_bits(lmk->regmap, in lmk04832_clkout_prepare()
1223 LMK04832_REG_CLKOUT_CTRL2(clkout->id), in lmk04832_clkout_prepare()
1228 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), in lmk04832_clkout_prepare()
1234 ret = regmap_update_bits(lmk->regmap, in lmk04832_clkout_prepare()
1235 LMK04832_REG_CLKOUT_CTRL4(clkout->id), in lmk04832_clkout_prepare()
1241 return regmap_update_bits(lmk->regmap, in lmk04832_clkout_prepare()
1242 LMK04832_REG_CLKOUT_FMT(clkout->id), in lmk04832_clkout_prepare()
1243 LMK04832_BIT_CLKOUT_FMT(clkout->id), in lmk04832_clkout_prepare()
1244 clkout->format << 4 * (clkout->id % 2)); in lmk04832_clkout_prepare()
1249 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); in lmk04832_clkout_unprepare() local
1250 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_unprepare()
1252 regmap_update_bits(lmk->regmap, LMK04832_REG_CLKOUT_FMT(clkout->id), in lmk04832_clkout_unprepare()
1253 LMK04832_BIT_CLKOUT_FMT(clkout->id), in lmk04832_clkout_unprepare()
1259 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); in lmk04832_clkout_set_parent() local
1260 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_set_parent()
1262 return regmap_update_bits(lmk->regmap, in lmk04832_clkout_set_parent()
1263 LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), in lmk04832_clkout_set_parent()
1271 struct lmk_clkout *clkout = container_of(hw, struct lmk_clkout, hw); in lmk04832_clkout_get_parent() local
1272 struct lmk04832 *lmk = clkout->lmk; in lmk04832_clkout_get_parent()
1276 ret = regmap_read(lmk->regmap, LMK04832_REG_CLKOUT_SRC_MUX(clkout->id), in lmk04832_clkout_get_parent()
1295 char name[] = "lmk-clkoutXX"; in lmk04832_register_clkout()
1296 char dclk_name[] = "lmk-dclkXX_YY"; in lmk04832_register_clkout()
1303 sprintf(dclk_name, "lmk-dclk%02d_%02d", num, num + 1); in lmk04832_register_clkout()
1305 parent_names[0] = clk_hw_get_name(&lmk->vco); in lmk04832_register_clkout()
1311 lmk->dclk[dclk_num].id = num; in lmk04832_register_clkout()
1312 lmk->dclk[dclk_num].lmk = lmk; in lmk04832_register_clkout()
1313 lmk->dclk[dclk_num].hw.init = &init; in lmk04832_register_clkout()
1315 ret = devm_clk_hw_register(lmk->dev, &lmk->dclk[dclk_num].hw); in lmk04832_register_clkout()
1319 sprintf(dclk_name, "lmk-dclk%02d_%02d", num - 1, num); in lmk04832_register_clkout()
1322 if (of_property_read_string_index(lmk->dev->of_node, in lmk04832_register_clkout()
1323 "clock-output-names", in lmk04832_register_clkout()
1325 sprintf(name, "lmk-clkout%02d", num); in lmk04832_register_clkout()
1330 parent_names[1] = clk_hw_get_name(&lmk->sclk); in lmk04832_register_clkout()
1336 lmk->clkout[num].id = num; in lmk04832_register_clkout()
1337 lmk->clkout[num].lmk = lmk; in lmk04832_register_clkout()
1338 lmk->clkout[num].hw.init = &init; in lmk04832_register_clkout()
1339 lmk->clk_data->hws[num] = &lmk->clkout[num].hw; in lmk04832_register_clkout()
1342 regmap_update_bits(lmk->regmap, in lmk04832_register_clkout()
1346 lmk->clkout[num].sysref)); in lmk04832_register_clkout()
1348 return devm_clk_hw_register(lmk->dev, &lmk->clkout[num].hw); in lmk04832_register_clkout()
1360 dev_info(lmk->dev, "setting up 4-wire mode\n"); in lmk04832_set_spi_rdbk()
1361 ret = regmap_write(lmk->regmap, LMK04832_REG_RST3W, in lmk04832_set_spi_rdbk()
1384 return -EINVAL; in lmk04832_set_spi_rdbk()
1387 return regmap_write(lmk->regmap, reg, val); in lmk04832_set_spi_rdbk()
1400 info = &lmk04832_device_info[spi_get_device_id(spi)->driver_data]; in lmk04832_probe()
1402 lmk = devm_kzalloc(&spi->dev, sizeof(struct lmk04832), GFP_KERNEL); in lmk04832_probe()
1404 return -ENOMEM; in lmk04832_probe()
1406 lmk->dev = &spi->dev; in lmk04832_probe()
1408 lmk->oscin = devm_clk_get_enabled(lmk->dev, "oscin"); in lmk04832_probe()
1409 if (IS_ERR(lmk->oscin)) { in lmk04832_probe()
1410 dev_err(lmk->dev, "failed to get oscin clock\n"); in lmk04832_probe()
1411 return PTR_ERR(lmk->oscin); in lmk04832_probe()
1414 lmk->reset_gpio = devm_gpiod_get_optional(&spi->dev, "reset", in lmk04832_probe()
1417 lmk->dclk = devm_kcalloc(lmk->dev, info->num_channels >> 1, in lmk04832_probe()
1419 if (!lmk->dclk) { in lmk04832_probe()
1420 ret = -ENOMEM; in lmk04832_probe()
1424 lmk->clkout = devm_kcalloc(lmk->dev, info->num_channels, in lmk04832_probe()
1425 sizeof(*lmk->clkout), GFP_KERNEL); in lmk04832_probe()
1426 if (!lmk->clkout) { in lmk04832_probe()
1427 ret = -ENOMEM; in lmk04832_probe()
1431 lmk->clk_data = devm_kzalloc(lmk->dev, struct_size(lmk->clk_data, hws, in lmk04832_probe()
1432 info->num_channels), in lmk04832_probe()
1434 if (!lmk->clk_data) { in lmk04832_probe()
1435 ret = -ENOMEM; in lmk04832_probe()
1439 device_property_read_u32(lmk->dev, "ti,vco-hz", &lmk->vco_rate); in lmk04832_probe()
1441 lmk->sysref_ddly = 8; in lmk04832_probe()
1442 device_property_read_u32(lmk->dev, "ti,sysref-ddly", &lmk->sysref_ddly); in lmk04832_probe()
1444 lmk->sysref_mux = LMK04832_VAL_SYSREF_MUX_CONTINUOUS; in lmk04832_probe()
1445 device_property_read_u32(lmk->dev, "ti,sysref-mux", in lmk04832_probe()
1446 &lmk->sysref_mux); in lmk04832_probe()
1448 lmk->sync_mode = LMK04832_VAL_SYNC_MODE_OFF; in lmk04832_probe()
1449 device_property_read_u32(lmk->dev, "ti,sync-mode", in lmk04832_probe()
1450 &lmk->sync_mode); in lmk04832_probe()
1452 lmk->sysref_pulse_cnt = 4; in lmk04832_probe()
1453 device_property_read_u32(lmk->dev, "ti,sysref-pulse-count", in lmk04832_probe()
1454 &lmk->sysref_pulse_cnt); in lmk04832_probe()
1456 for_each_child_of_node(lmk->dev->of_node, child) { in lmk04832_probe()
1461 dev_err(lmk->dev, "missing reg property in child: %s\n", in lmk04832_probe()
1462 child->full_name); in lmk04832_probe()
1467 of_property_read_u32(child, "ti,clkout-fmt", in lmk04832_probe()
1468 &lmk->clkout[reg].format); in lmk04832_probe()
1470 if (lmk->clkout[reg].format >= 0x0a && reg % 2 == 0 in lmk04832_probe()
1472 dev_err(lmk->dev, "invalid format for clkout%02d\n", in lmk04832_probe()
1475 lmk->clkout[reg].sysref = in lmk04832_probe()
1476 of_property_read_bool(child, "ti,clkout-sysref"); in lmk04832_probe()
1479 lmk->regmap = devm_regmap_init_spi(spi, ®map_config); in lmk04832_probe()
1480 if (IS_ERR(lmk->regmap)) { in lmk04832_probe()
1481 dev_err(lmk->dev, "%s: regmap allocation failed: %ld\n", in lmk04832_probe()
1483 __func__, PTR_ERR(lmk->regmap)); in lmk04832_probe()
1484 ret = PTR_ERR(lmk->regmap); in lmk04832_probe()
1488 regmap_write(lmk->regmap, LMK04832_REG_RST3W, LMK04832_BIT_RESET); in lmk04832_probe()
1490 if (!(spi->mode & SPI_3WIRE)) { in lmk04832_probe()
1491 device_property_read_u32(lmk->dev, "ti,spi-4wire-rdbk", in lmk04832_probe()
1498 regmap_bulk_read(lmk->regmap, LMK04832_REG_ID_PROD_MSB, &tmp, 3); in lmk04832_probe()
1499 if ((tmp[0] << 8 | tmp[1]) != info->pid || tmp[2] != info->maskrev) { in lmk04832_probe()
1500 dev_err(lmk->dev, "unsupported device type: pid 0x%04x, maskrev 0x%02x\n", in lmk04832_probe()
1502 ret = -EINVAL; in lmk04832_probe()
1508 dev_err(lmk->dev, "failed to init device clock path\n"); in lmk04832_probe()
1512 if (lmk->vco_rate) { in lmk04832_probe()
1513 dev_info(lmk->dev, "setting VCO rate to %u Hz\n", lmk->vco_rate); in lmk04832_probe()
1514 ret = clk_set_rate(lmk->vco.clk, lmk->vco_rate); in lmk04832_probe()
1516 dev_err(lmk->dev, "failed to set VCO rate\n"); in lmk04832_probe()
1523 dev_err(lmk->dev, "failed to init SYNC/SYSREF clock path\n"); in lmk04832_probe()
1527 for (i = 0; i < info->num_channels; i++) { in lmk04832_probe()
1530 dev_err(lmk->dev, "failed to register clk %d\n", i); in lmk04832_probe()
1535 lmk->clk_data->num = info->num_channels; in lmk04832_probe()
1536 ret = devm_of_clk_add_hw_provider(lmk->dev, of_clk_hw_onecell_get, in lmk04832_probe()
1537 lmk->clk_data); in lmk04832_probe()
1539 dev_err(lmk->dev, "failed to add provider (%d)\n", ret); in lmk04832_probe()