Lines Matching full:pll1
300 * PLLs configuration: by default PLL0 runs at 780 MHz and PLL1 at 299 MHz.
302 * rate divided by 2. Set PLL1 to 390 MHz so that the third SRAM bank has the
576 /* PLL0 and PLL1 only have IN0 as parent */ in k210_register_plls()
582 ret = k210_register_pll(np, ksc, K210_PLL1, "pll1", 1, &k210_pll_ops); in k210_register_plls()
584 pr_err("%pOFP: register PLL1 failed\n", np); in k210_register_plls()
588 /* PLL2 has IN0, PLL0 and PLL1 as parents */ in k210_register_plls()
998 * Enable PLL1 to be able to use the AI SRAM.
1002 struct k210_pll pll1; in k210_clk_early_init() local
1007 /* Startup PLL1 to enable the aisram bank for general memory use */ in k210_clk_early_init()
1008 k210_init_pll(regs, K210_PLL1, &pll1); in k210_clk_early_init()
1009 k210_pll_enable_hw(regs, &pll1); in k210_clk_early_init()