Lines Matching +full:ep9301 +full:- +full:pwm
1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Based on a rewrite of arch/arm/mach-ep93xx/clock.c:
13 #include <linux/clk-provider.h>
20 #include <dt-bindings/clock/cirrus,ep9301-syscon.h>
105 return container_of(clk, struct ep93xx_clk_priv, reg[clk->idx]);
110 struct ep93xx_regmap_adev *aux = priv->aux_dev;
112 aux->write(aux->map, aux->lock, reg, val);
121 regmap_read(priv->map, clk->reg, &val);
123 return !!(val & BIT(clk->bit_idx));
132 guard(spinlock_irqsave)(&priv->lock);
134 regmap_read(priv->map, clk->reg, &val);
135 val |= BIT(clk->bit_idx);
137 ep93xx_clk_write(priv, clk->reg, val);
148 guard(spinlock_irqsave)(&priv->lock);
150 regmap_read(priv->map, clk->reg, &val);
151 val &= ~BIT(clk->bit_idx);
153 ep93xx_clk_write(priv, clk->reg, val);
178 clk->reg = reg;
179 clk->bit_idx = bit_idx;
180 clk->hw.init = &init;
182 return devm_clk_hw_register(priv->dev, &clk->hw);
191 regmap_read(priv->map, clk->reg, &val);
212 return -EINVAL;
214 guard(spinlock_irqsave)(&priv->lock);
216 regmap_read(priv->map, clk->reg, &val);
221 ep93xx_clk_write(priv, clk->reg, val);
236 unsigned long rate = req->rate;
249 * http://be-a-maverick.com/en/pubs/appNote/AN269REV1.pdf
274 return -EINVAL;
276 req->best_parent_rate = parent_rate_best;
277 req->best_parent_hw = parent_best;
278 req->rate = best_rate;
291 regmap_read(priv->map, clk->reg, &val);
309 regmap_read(priv->map, clk->reg, &val);
318 if (abs(actual_rate - rate) < rate_err) {
319 npdiv = pdiv - 3;
321 rate_err = abs(actual_rate - rate);
326 return -EINVAL;
337 ep93xx_clk_write(priv, clk->reg, val);
369 clk->reg = reg;
370 clk->bit_idx = bit_idx;
371 clk->hw.init = &init;
373 return devm_clk_hw_register(priv->dev, &clk->hw);
384 regmap_read(priv->map, clk->reg, &val);
385 index = (val & clk->mask) >> clk->shift;
386 if (index >= clk->num_div)
389 return DIV_ROUND_CLOSEST(parent_rate, clk->div[index]);
399 for (i = 0; i < clk->num_div; i++) {
400 if ((rate * clk->div[i]) == *parent_rate)
403 now = DIV_ROUND_CLOSEST(*parent_rate, clk->div[i]);
419 regmap_read(priv->map, clk->reg, &val);
420 val &= ~clk->mask;
421 for (i = 0; i < clk->num_div; i++)
422 if (rate == DIV_ROUND_CLOSEST(parent_rate, clk->div[i]))
425 if (i == clk->num_div)
426 return -EINVAL;
428 val |= i << clk->shift;
430 ep93xx_clk_write(priv, clk->reg, val);
463 clk->reg = reg;
464 clk->bit_idx = enable_bit;
465 clk->mask = GENMASK(shift + width - 1, shift);
466 clk->shift = shift;
467 clk->div = clk_divisors;
468 clk->num_div = num_div;
469 clk->hw.init = &init;
471 return devm_clk_hw_register(priv->dev, &clk->hw);
493 regmap_read(priv->map, EP93XX_SYSCON_PWRCNT, &val);
499 priv->fixed[EP93XX_CLK_UART] =
500 devm_clk_hw_register_fixed_factor_index(priv->dev, "uart",
503 parent_data.hw = priv->fixed[EP93XX_CLK_UART];
507 idx = ep93xx_uarts[i].idx - EP93XX_CLK_UART1;
508 clk = &priv->reg[idx];
509 clk->idx = idx;
516 return dev_err_probe(priv->dev, ret,
543 parent_data.hw = priv->fixed[EP93XX_CLK_HCLK];
546 priv->fixed[idx] = devm_clk_hw_register_gate_parent_data(priv->dev,
549 priv->base + EP93XX_SYSCON_PWRCNT,
552 &priv->lock);
553 if (IS_ERR(priv->fixed[idx]))
554 return PTR_ERR(priv->fixed[idx]);
563 unsigned int idx = clkspec->args[0];
566 return priv->fixed[idx];
569 return &priv->reg[idx - EP93XX_CLK_UART1].hw;
571 return ERR_PTR(-EINVAL);
595 struct device *dev = priv->dev;
600 regmap_read(priv->map, EP93XX_SYSCON_CLKSET1, &value);
612 priv->fixed[EP93XX_CLK_PLL1] = pll1;
623 priv->fixed[EP93XX_CLK_FCLK] = hw;
629 priv->fixed[EP93XX_CLK_HCLK] = hw;
635 priv->fixed[EP93XX_CLK_PCLK] = hw;
638 regmap_read(priv->map, EP93XX_SYSCON_CLKSET2, &value);
651 priv->fixed[EP93XX_CLK_PLL2] = hw;
664 struct device *dev = &adev->dev;
674 return -ENOMEM;
676 spin_lock_init(&priv->lock);
677 priv->dev = dev;
678 priv->aux_dev = rdev;
679 priv->map = rdev->map;
680 priv->base = rdev->base;
686 regmap_read(priv->map, EP93XX_SYSCON_CLKSET2, &value);
689 priv->fixed[EP93XX_CLK_PLL2], 0, 1,
694 priv->fixed[EP93XX_CLK_USB] = hw;
704 clk_spi_div = id->driver_data;
705 hw = devm_clk_hw_register_fixed_factor_index(dev, "ep93xx-spi.0",
711 priv->fixed[EP93XX_CLK_SPI] = hw;
713 /* PWM clock */
719 priv->fixed[EP93XX_CLK_PWM] = hw;
722 pdata.hw = priv->fixed[EP93XX_CLK_USB];
723 hw = devm_clk_hw_register_gate_parent_data(priv->dev, "ohci-platform", &pdata,
724 0, priv->base + EP93XX_SYSCON_PWRCNT,
726 &priv->lock);
730 priv->fixed[EP93XX_CLK_USB] = hw;
733 ddiv_pdata[1].hw = priv->fixed[EP93XX_CLK_PLL1];
734 ddiv_pdata[2].hw = priv->fixed[EP93XX_CLK_PLL2];
737 idx = EP93XX_CLK_ADC - EP93XX_CLK_UART1;
738 clk = &priv->reg[idx];
739 clk->idx = idx;
740 ret = ep93xx_register_div(clk, "ep93xx-adc", &xtali,
750 idx = EP93XX_CLK_KEYPAD - EP93XX_CLK_UART1;
751 clk = &priv->reg[idx];
752 clk->idx = idx;
753 ret = ep93xx_register_div(clk, "ep93xx-keypad", &xtali,
765 * ENA - Enable CLK divider.
766 * PDIV - 00 - Disable clock
767 * VDIV - at least 2
771 regmap_read(priv->map, EP93XX_SYSCON_VIDCLKDIV, &value);
776 regmap_read(priv->map, EP93XX_SYSCON_I2SCLKDIV, &value);
788 idx = EP93XX_CLK_VIDEO - EP93XX_CLK_UART1;
789 clk = &priv->reg[idx];
790 clk->idx = idx;
791 ret = ep93xx_clk_register_ddiv(clk, "ep93xx-fb",
797 idx = EP93XX_CLK_I2S_MCLK - EP93XX_CLK_UART1;
798 clk = &priv->reg[idx];
799 clk->idx = idx;
806 idx = EP93XX_CLK_I2S_SCLK - EP93XX_CLK_UART1;
807 clk = &priv->reg[idx];
808 clk->idx = idx;
809 pdata.hw = &priv->reg[EP93XX_CLK_I2S_MCLK - EP93XX_CLK_UART1].hw;
819 idx = EP93XX_CLK_I2S_LRCLK - EP93XX_CLK_UART1;
820 clk = &priv->reg[idx];
821 clk->idx = idx;
822 pdata.hw = &priv->reg[EP93XX_CLK_I2S_SCLK - EP93XX_CLK_UART1].hw;
832 return devm_of_clk_add_hw_provider(priv->dev, of_clk_ep93xx_get, priv);
836 { .name = "soc_ep93xx.clk-ep93xx", .driver_data = 2, },
837 { .name = "soc_ep93xx.clk-ep93xx.e2", .driver_data = 1, },