1 // SPDX-License-Identifier: GPL-2.0-only
4 #include <linux/clk-provider.h>
10 #include <linux/reset-controller.h>
11 #include <dt-bindings/clock/en7523-clk.h>
12 #include <dt-bindings/reset/airoha,en7581-reset.h>
35 /* EN7581 */
88 /* EN7581 */
351 	if (!desc->base_bits)  in en7523_get_base_rate()
352 		return desc->base_value;  in en7523_get_base_rate()
354 	val >>= desc->base_shift;  in en7523_get_base_rate()
355 	val &= (1 << desc->base_bits) - 1;  in en7523_get_base_rate()
357 	if (val >= desc->n_base_values)  in en7523_get_base_rate()
360 	return desc->base_values[val];  in en7523_get_base_rate()
365 	if (!desc->div_bits)  in en7523_get_div()
368 	val >>= desc->div_shift;  in en7523_get_div()
369 	val &= (1 << desc->div_bits) - 1;  in en7523_get_div()
371 	if (!val && desc->div_val0)  in en7523_get_div()
372 		return desc->div_val0;  in en7523_get_div()
374 	return (val + desc->div_offset) * desc->div_step;  in en7523_get_div()
381 	return !!(readl(cg->base + REG_PCI_CONTROL) & REG_PCI_CONTROL_REFCLK_EN1);  in en7523_pci_is_enabled()
387 	void __iomem *np_base = cg->base;  in en7523_pci_prepare()
426 	void __iomem *np_base = cg->base;  in en7523_pci_unprepare()
440 		.ops = &soc_data->pcie_ops,  in en7523_register_pcie_clk()
448 	cg->base = np_base;  in en7523_register_pcie_clk()
449 	cg->hw.init = &init;  in en7523_register_pcie_clk()
451 	if (init.ops->unprepare)  in en7523_register_pcie_clk()
452 		init.ops->unprepare(&cg->hw);  in en7523_register_pcie_clk()
454 	if (clk_hw_register(dev, &cg->hw))  in en7523_register_pcie_clk()
457 	return &cg->hw;  in en7523_register_pcie_clk()
466 	val = readl(cg->base + REG_PCI_CONTROL);  in en7581_pci_is_enabled()
473 	void __iomem *np_base = cg->base;  in en7581_pci_enable()
489 	void __iomem *np_base = cg->base;  in en7581_pci_disable()
507 	clk_data->num = EN7523_NUM_CLOCKS;  in en7523_register_clocks()
511 		u32 reg = desc->div_reg ? desc->div_reg : desc->base_reg;  in en7523_register_clocks()
512 		u32 val = readl(base + desc->base_reg);  in en7523_register_clocks()
518 		hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate);  in en7523_register_clocks()
521 			       desc->name, PTR_ERR(hw));  in en7523_register_clocks()
525 		clk_data->hws[desc->id] = hw;  in en7523_register_clocks()
529 	clk_data->hws[EN7523_CLK_PCIE] = hw;  in en7523_register_clocks()
545 	en7523_register_clocks(&pdev->dev, clk_data, base, np_base);  in en7523_clk_hw_init()
559 		u32 val, reg = desc->div_reg ? desc->div_reg : desc->base_reg;  in en7581_register_clocks()
562 		err = regmap_read(map, desc->base_reg, &val);  in en7581_register_clocks()
565 			       desc->name, err);  in en7581_register_clocks()
573 			       desc->name, err);  in en7581_register_clocks()
578 		hw = clk_hw_register_fixed_rate(dev, desc->name, NULL, 0, rate);  in en7581_register_clocks()
581 			       desc->name, PTR_ERR(hw));  in en7581_register_clocks()
585 		clk_data->hws[desc->id] = hw;  in en7581_register_clocks()
589 	clk_data->hws[EN7523_CLK_PCIE] = hw;  in en7581_register_clocks()
591 	clk_data->num = EN7523_NUM_CLOCKS;  in en7581_register_clocks()
598 	void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];  in en7523_reset_update()
627 	void __iomem *addr = rst_data->base + rst_data->bank_ofs[id / RST_NR_PER_BANK];  in en7523_reset_status()
637 	if (reset_spec->args[0] >= rcdev->nr_resets)  in en7523_reset_xlate()
638 		return -EINVAL;  in en7523_reset_xlate()
640 	return rst_data->idx_map[reset_spec->args[0]];  in en7523_reset_xlate()
655 		return -ENOMEM;  in en7581_reset_register()
657 	rst_data->bank_ofs = en7581_rst_ofs;  in en7581_reset_register()
658 	rst_data->idx_map = en7581_rst_map;  in en7581_reset_register()
659 	rst_data->base = base;  in en7581_reset_register()
661 	rst_data->rcdev.nr_resets = ARRAY_SIZE(en7581_rst_map);  in en7581_reset_register()
662 	rst_data->rcdev.of_xlate = en7523_reset_xlate;  in en7581_reset_register()
663 	rst_data->rcdev.ops = &en7581_reset_ops;  in en7581_reset_register()
664 	rst_data->rcdev.of_node = dev->of_node;  in en7581_reset_register()
665 	rst_data->rcdev.of_reset_n_cells = 1;  in en7581_reset_register()
666 	rst_data->rcdev.owner = THIS_MODULE;  in en7581_reset_register()
667 	rst_data->rcdev.dev = dev;  in en7581_reset_register()
669 	return devm_reset_controller_register(dev, &rst_data->rcdev);  in en7581_reset_register()
679 	map = syscon_regmap_lookup_by_compatible("airoha,en7581-chip-scu");  in en7581_clk_hw_init()
687 	en7581_register_clocks(&pdev->dev, clk_data, map, base);  in en7581_clk_hw_init()
695 	return en7581_reset_register(&pdev->dev, base);  in en7581_clk_hw_init()
700 	struct device_node *node = pdev->dev.of_node;  in en7523_clk_probe()
705 	clk_data = devm_kzalloc(&pdev->dev,  in en7523_clk_probe()
709 		return -ENOMEM;  in en7523_clk_probe()
711 	soc_data = device_get_match_data(&pdev->dev);  in en7523_clk_probe()
712 	r = soc_data->hw_init(pdev, clk_data);  in en7523_clk_probe()
738 	{ .compatible = "airoha,en7523-scu", .data = &en7523_data },
739 	{ .compatible = "airoha,en7581-scu", .data = &en7581_data },
746 		.name = "clk-en7523",