Lines Matching +full:center +full:- +full:spread
5 * Y4/Y5 to PLL2, and so on. PLL frequency is set on a first-come-first-serve
14 #include <linux/clk-provider.h>
54 u16 pdiv; /* 1..127 for Y2-Y9; 1..1023 for Y1 */
92 return cdce925_pll_calculate_rate(parent_rate, data->n, data->m); in cdce925_pll_recalc_rate()
136 cdce925_pll_find_rate(req->rate, req->best_parent_rate, &n, &m); in cdce925_pll_determine_rate()
137 req->rate = (long)cdce925_pll_calculate_rate(req->best_parent_rate, n, m); in cdce925_pll_determine_rate()
148 data->m = 0; /* Bypass mode */ in cdce925_pll_set_rate()
149 data->n = 0; in cdce925_pll_set_rate()
156 return -EINVAL; in cdce925_pll_set_rate()
162 return -EINVAL; in cdce925_pll_set_rate()
165 cdce925_pll_find_rate(rate, parent_rate, &data->n, &data->m); in cdce925_pll_set_rate()
170 /* calculate p = max(0, 4 - int(log2 (n/m))) */
181 --p; in cdce925_pll_calc_p()
189 struct clk *parent = clk_get_parent(hw->clk); in cdce925_pll_calc_range_bits()
207 u16 n = data->n; in cdce925_pll_prepare()
208 u16 m = data->m; in cdce925_pll_prepare()
213 u8 pll[4]; /* Bits are spread out over 4 byte registers */ in cdce925_pll_prepare()
214 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_prepare()
219 regmap_update_bits(data->chip->regmap, in cdce925_pll_prepare()
223 /* p = max(0, 4 - int(log2 (n/m))) */ in cdce925_pll_prepare()
231 return -EINVAL; in cdce925_pll_prepare()
233 r = nn - (m*q); in cdce925_pll_prepare()
236 return -EINVAL; in cdce925_pll_prepare()
248 regmap_write(data->chip->regmap, in cdce925_pll_prepare()
251 regmap_update_bits(data->chip->regmap, in cdce925_pll_prepare()
261 u8 reg_ofs = data->index * CDCE925_OFFSET_PLL; in cdce925_pll_unprepare()
263 regmap_update_bits(data->chip->regmap, in cdce925_pll_unprepare()
278 switch (data->index) { in cdce925_clk_set_pdiv()
280 regmap_update_bits(data->chip->regmap, in cdce925_clk_set_pdiv()
283 regmap_write(data->chip->regmap, 0x03, pdiv & 0xFF); in cdce925_clk_set_pdiv()
286 regmap_update_bits(data->chip->regmap, 0x16, 0x7F, pdiv); in cdce925_clk_set_pdiv()
289 regmap_update_bits(data->chip->regmap, 0x17, 0x7F, pdiv); in cdce925_clk_set_pdiv()
292 regmap_update_bits(data->chip->regmap, 0x26, 0x7F, pdiv); in cdce925_clk_set_pdiv()
295 regmap_update_bits(data->chip->regmap, 0x27, 0x7F, pdiv); in cdce925_clk_set_pdiv()
298 regmap_update_bits(data->chip->regmap, 0x36, 0x7F, pdiv); in cdce925_clk_set_pdiv()
301 regmap_update_bits(data->chip->regmap, 0x37, 0x7F, pdiv); in cdce925_clk_set_pdiv()
304 regmap_update_bits(data->chip->regmap, 0x46, 0x7F, pdiv); in cdce925_clk_set_pdiv()
307 regmap_update_bits(data->chip->regmap, 0x47, 0x7F, pdiv); in cdce925_clk_set_pdiv()
314 switch (data->index) { in cdce925_clk_activate()
316 regmap_update_bits(data->chip->regmap, in cdce925_clk_activate()
321 regmap_update_bits(data->chip->regmap, 0x14, 0x03, 0x03); in cdce925_clk_activate()
325 regmap_update_bits(data->chip->regmap, 0x24, 0x03, 0x03); in cdce925_clk_activate()
329 regmap_update_bits(data->chip->regmap, 0x34, 0x03, 0x03); in cdce925_clk_activate()
333 regmap_update_bits(data->chip->regmap, 0x44, 0x03, 0x03); in cdce925_clk_activate()
342 cdce925_clk_set_pdiv(data, data->pdiv); in cdce925_clk_prepare()
360 if (data->pdiv) in cdce925_clk_recalc_rate()
361 return parent_rate / data->pdiv; in cdce925_clk_recalc_rate()
385 struct clk *pll = clk_get_parent(hw->clk); in cdce925_clk_best_parent_rate()
413 rate_error = abs((long)actual_rate - (long)rate); in cdce925_clk_best_parent_rate()
428 unsigned long l_parent_rate = req->best_parent_rate; in cdce925_clk_determine_rate()
429 u16 divider = cdce925_calc_divider(req->rate, l_parent_rate); in cdce925_clk_determine_rate()
431 if (l_parent_rate / divider != req->rate) { in cdce925_clk_determine_rate()
432 l_parent_rate = cdce925_clk_best_parent_rate(hw, req->rate); in cdce925_clk_determine_rate()
433 divider = cdce925_calc_divider(req->rate, l_parent_rate); in cdce925_clk_determine_rate()
434 req->best_parent_rate = l_parent_rate; in cdce925_clk_determine_rate()
438 req->rate = (long)(l_parent_rate / divider); in cdce925_clk_determine_rate()
440 req->rate = 0; in cdce925_clk_determine_rate()
450 data->pdiv = cdce925_calc_divider(rate, parent_rate); in cdce925_clk_set_rate()
475 if (divider > 0x3FF) /* Y1 has 10-bit divider */ in cdce925_y1_calc_divider()
484 unsigned long l_parent_rate = req->best_parent_rate; in cdce925_clk_y1_determine_rate()
485 u16 divider = cdce925_y1_calc_divider(req->rate, l_parent_rate); in cdce925_clk_y1_determine_rate()
488 req->rate = (long)(l_parent_rate / divider); in cdce925_clk_y1_determine_rate()
490 req->rate = 0; in cdce925_clk_y1_determine_rate()
500 data->pdiv = cdce925_y1_calc_divider(rate, parent_rate); in cdce925_clk_y1_set_rate()
525 return -ENOTSUPP; in cdce925_regmap_i2c_write()
531 dev_dbg(&i2c->dev, "%s(%zu) %#x %#x\n", __func__, count, in cdce925_regmap_i2c_write()
540 return -EIO; in cdce925_regmap_i2c_write()
553 return -ENOTSUPP; in cdce925_regmap_i2c_read()
555 xfer[0].addr = i2c->addr; in cdce925_regmap_i2c_read()
569 xfer[1].addr = i2c->addr; in cdce925_regmap_i2c_read()
574 ret = i2c_transfer(i2c->adapter, xfer, 2); in cdce925_regmap_i2c_read()
576 dev_dbg(&i2c->dev, "%s(%zu, %zu) %#x %#x\n", __func__, in cdce925_regmap_i2c_read()
582 return -EIO; in cdce925_regmap_i2c_read()
589 unsigned int idx = clkspec->args[0]; in of_clk_cdce925_get()
591 if (idx >= ARRAY_SIZE(data->clk)) { in of_clk_cdce925_get()
593 return ERR_PTR(-EINVAL); in of_clk_cdce925_get()
596 return &data->clk[idx].hw; in of_clk_cdce925_get()
620 struct device_node *node = client->dev.of_node; in cdce925_probe()
636 dev_dbg(&client->dev, "%s\n", __func__); in cdce925_probe()
638 err = cdce925_regulator_enable(&client->dev, "vdd"); in cdce925_probe()
642 err = cdce925_regulator_enable(&client->dev, "vddout"); in cdce925_probe()
646 data = devm_kzalloc(&client->dev, sizeof(*data), GFP_KERNEL); in cdce925_probe()
648 return -ENOMEM; in cdce925_probe()
650 data->i2c_client = client; in cdce925_probe()
651 data->chip_info = i2c_get_match_data(client); in cdce925_probe()
653 data->chip_info->num_plls * 0x10 - 1; in cdce925_probe()
654 data->regmap = devm_regmap_init(&client->dev, ®map_cdce925_bus, in cdce925_probe()
655 &client->dev, &config); in cdce925_probe()
656 if (IS_ERR(data->regmap)) { in cdce925_probe()
657 dev_err(&client->dev, "failed to allocate register map\n"); in cdce925_probe()
658 return PTR_ERR(data->regmap); in cdce925_probe()
664 dev_err(&client->dev, "missing parent clock\n"); in cdce925_probe()
665 return -ENODEV; in cdce925_probe()
667 dev_dbg(&client->dev, "parent is: %s\n", parent_name); in cdce925_probe()
669 if (of_property_read_u32(node, "xtal-load-pf", &value) == 0) in cdce925_probe()
670 regmap_write(data->regmap, in cdce925_probe()
673 regmap_update_bits(data->regmap, CDCE925_REG_GLOBAL1, BIT(4), 0); in cdce925_probe()
676 regmap_update_bits(data->regmap, 0x02, BIT(7), 0); in cdce925_probe()
684 for (i = 0; i < data->chip_info->num_plls; ++i) { in cdce925_probe()
686 client->dev.of_node, i); in cdce925_probe()
688 err = -ENOMEM; in cdce925_probe()
692 data->pll[i].chip = data; in cdce925_probe()
693 data->pll[i].hw.init = &init; in cdce925_probe()
694 data->pll[i].index = i; in cdce925_probe()
695 err = devm_clk_hw_register(&client->dev, &data->pll[i].hw); in cdce925_probe()
697 dev_err(&client->dev, "Failed register PLL %d\n", i); in cdce925_probe()
705 "clock-frequency", &value)) { in cdce925_probe()
706 err = clk_set_rate(data->pll[i].hw.clk, value); in cdce925_probe()
708 dev_err(&client->dev, in cdce925_probe()
713 "spread-spectrum", &value)) { in cdce925_probe()
715 "spread-spectrum-center") ? 0x80 : 0x00; in cdce925_probe()
716 regmap_update_bits(data->regmap, in cdce925_probe()
719 regmap_update_bits(data->regmap, in cdce925_probe()
731 init.name = kasprintf(GFP_KERNEL, "%pOFn.Y1", client->dev.of_node); in cdce925_probe()
733 err = -ENOMEM; in cdce925_probe()
736 data->clk[0].chip = data; in cdce925_probe()
737 data->clk[0].hw.init = &init; in cdce925_probe()
738 data->clk[0].index = 0; in cdce925_probe()
739 data->clk[0].pdiv = 1; in cdce925_probe()
740 err = devm_clk_hw_register(&client->dev, &data->clk[0].hw); in cdce925_probe()
743 dev_err(&client->dev, "clock registration Y1 failed\n"); in cdce925_probe()
751 for (i = 1; i < data->chip_info->num_outputs; ++i) { in cdce925_probe()
753 client->dev.of_node, i+1); in cdce925_probe()
755 err = -ENOMEM; in cdce925_probe()
758 data->clk[i].chip = data; in cdce925_probe()
759 data->clk[i].hw.init = &init; in cdce925_probe()
760 data->clk[i].index = i; in cdce925_probe()
761 data->clk[i].pdiv = 1; in cdce925_probe()
784 err = devm_clk_hw_register(&client->dev, &data->clk[i].hw); in cdce925_probe()
787 dev_err(&client->dev, "clock registration failed\n"); in cdce925_probe()
793 err = of_clk_add_hw_provider(client->dev.of_node, of_clk_cdce925_get, in cdce925_probe()
796 dev_err(&client->dev, "unable to add OF clock provider\n"); in cdce925_probe()
801 for (i = 0; i < data->chip_info->num_plls; ++i) in cdce925_probe()