1 // SPDX-License-Identifier: GPL-2.0+
3  * Bitmain BM1880 SoC clock driver
9 #include <linux/clk-provider.h>
17 #include <dt-bindings/clock/bm1880-clock.h>
156 		.mux_shift = -1,					\
168 		.div_shift = -1,					\
499 	regval = readl(pll_hw->base + pll_hw->pll.reg);  in bm1880_pll_recalc_rate()
515 	pll_clk->base = sys_base;  in bm1880_clk_register_pll()
516 	hw = &pll_clk->hw;  in bm1880_clk_register_pll()
530 	void __iomem *pll_base = data->pll_base;  in bm1880_clk_register_plls()
539 			       __func__, bm1880_clk->pll.name);  in bm1880_clk_register_plls()
543 		data->hw_data.hws[clks[i].pll.id] = hw;  in bm1880_clk_register_plls()
549 	while (i--)  in bm1880_clk_register_plls()
550 		clk_hw_unregister(data->hw_data.hws[clks[i].pll.id]);  in bm1880_clk_register_plls()
560 	void __iomem *sys_base = data->sys_base;  in bm1880_clk_register_mux()
577 		data->hw_data.hws[clks[i].id] = hw;  in bm1880_clk_register_mux()
583 	while (i--)  in bm1880_clk_register_mux()
584 		clk_hw_unregister_mux(data->hw_data.hws[clks[i].id]);  in bm1880_clk_register_mux()
593 	struct bm1880_div_clock *div = &div_hw->div;  in bm1880_clk_div_recalc_rate()
594 	void __iomem *reg_addr = div_hw->base + div->reg;  in bm1880_clk_div_recalc_rate()
599 		val = div->initval;  in bm1880_clk_div_recalc_rate()
601 		val = readl(reg_addr) >> div->shift;  in bm1880_clk_div_recalc_rate()
602 		val &= clk_div_mask(div->width);  in bm1880_clk_div_recalc_rate()
605 	rate = divider_recalc_rate(hw, parent_rate, val, div->table,  in bm1880_clk_div_recalc_rate()
606 				   div->flags, div->width);  in bm1880_clk_div_recalc_rate()
615 	struct bm1880_div_clock *div = &div_hw->div;  in bm1880_clk_div_round_rate()
616 	void __iomem *reg_addr = div_hw->base + div->reg;  in bm1880_clk_div_round_rate()
618 	if (div->flags & CLK_DIVIDER_READ_ONLY) {  in bm1880_clk_div_round_rate()
621 		val = readl(reg_addr) >> div->shift;  in bm1880_clk_div_round_rate()
622 		val &= clk_div_mask(div->width);  in bm1880_clk_div_round_rate()
624 		return divider_ro_round_rate(hw, rate, prate, div->table,  in bm1880_clk_div_round_rate()
625 					     div->width, div->flags,  in bm1880_clk_div_round_rate()
629 	return divider_round_rate(hw, rate, prate, div->table,  in bm1880_clk_div_round_rate()
630 				  div->width, div->flags);  in bm1880_clk_div_round_rate()
637 	struct bm1880_div_clock *div = &div_hw->div;  in bm1880_clk_div_set_rate()
638 	void __iomem *reg_addr = div_hw->base + div->reg;  in bm1880_clk_div_set_rate()
643 	value = divider_get_val(rate, parent_rate, div->table,  in bm1880_clk_div_set_rate()
644 				div->width, div_hw->div.flags);  in bm1880_clk_div_set_rate()
648 	if (div_hw->lock)  in bm1880_clk_div_set_rate()
649 		spin_lock_irqsave(div_hw->lock, flags);  in bm1880_clk_div_set_rate()
651 		__acquire(div_hw->lock);  in bm1880_clk_div_set_rate()
654 	val &= ~(clk_div_mask(div->width) << div_hw->div.shift);  in bm1880_clk_div_set_rate()
655 	val |= (u32)value << div->shift;  in bm1880_clk_div_set_rate()
658 	if (div_hw->lock)  in bm1880_clk_div_set_rate()
659 		spin_unlock_irqrestore(div_hw->lock, flags);  in bm1880_clk_div_set_rate()
661 		__release(div_hw->lock);  in bm1880_clk_div_set_rate()
678 	div_clk->div.flags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO;  in bm1880_clk_register_div()
679 	div_clk->base = sys_base;  in bm1880_clk_register_div()
680 	div_clk->lock = &bm1880_clk_lock;  in bm1880_clk_register_div()
682 	hw = &div_clk->hw;  in bm1880_clk_register_div()
695 	void __iomem *sys_base = data->sys_base;  in bm1880_clk_register_divs()
704 			       __func__, bm1880_clk->div.name);  in bm1880_clk_register_divs()
709 		data->hw_data.hws[id] = hw;  in bm1880_clk_register_divs()
715 	while (i--)  in bm1880_clk_register_divs()
716 		clk_hw_unregister(data->hw_data.hws[clks[i].div.id]);  in bm1880_clk_register_divs()
726 	void __iomem *sys_base = data->sys_base;  in bm1880_clk_register_gate()
742 		data->hw_data.hws[clks[i].id] = hw;  in bm1880_clk_register_gate()
748 	while (i--)  in bm1880_clk_register_gate()
749 		clk_hw_unregister_gate(data->hw_data.hws[clks[i].id]);  in bm1880_clk_register_gate()
768 	if (clks->mux_shift >= 0) {  in bm1880_clk_register_composite()
771 			return ERR_PTR(-ENOMEM);  in bm1880_clk_register_composite()
773 		mux->reg = sys_base + clks->mux_reg;  in bm1880_clk_register_composite()
774 		mux->mask = 1;  in bm1880_clk_register_composite()
775 		mux->shift = clks->mux_shift;  in bm1880_clk_register_composite()
776 		mux_hw = &mux->hw;  in bm1880_clk_register_composite()
778 		mux->lock = &bm1880_clk_lock;  in bm1880_clk_register_composite()
780 		parent_names = clks->parents;  in bm1880_clk_register_composite()
781 		num_parents = clks->num_parents;  in bm1880_clk_register_composite()
783 		parent = clks->parent;  in bm1880_clk_register_composite()
788 	if (clks->gate_shift >= 0) {  in bm1880_clk_register_composite()
791 			ret = -ENOMEM;  in bm1880_clk_register_composite()
795 		gate->reg = sys_base + clks->gate_reg;  in bm1880_clk_register_composite()
796 		gate->bit_idx = clks->gate_shift;  in bm1880_clk_register_composite()
797 		gate->lock = &bm1880_clk_lock;  in bm1880_clk_register_composite()
799 		gate_hw = &gate->hw;  in bm1880_clk_register_composite()
803 	if (clks->div_shift >= 0) {  in bm1880_clk_register_composite()
806 			ret = -ENOMEM;  in bm1880_clk_register_composite()
810 		div_hws->base = sys_base;  in bm1880_clk_register_composite()
811 		div_hws->div.reg = clks->div_reg;  in bm1880_clk_register_composite()
812 		div_hws->div.shift = clks->div_shift;  in bm1880_clk_register_composite()
813 		div_hws->div.width = clks->div_width;  in bm1880_clk_register_composite()
814 		div_hws->div.table = clks->table;  in bm1880_clk_register_composite()
815 		div_hws->div.initval = clks->div_initval;  in bm1880_clk_register_composite()
816 		div_hws->lock = &bm1880_clk_lock;  in bm1880_clk_register_composite()
817 		div_hws->div.flags = CLK_DIVIDER_ONE_BASED |  in bm1880_clk_register_composite()
820 		div_hw = &div_hws->hw;  in bm1880_clk_register_composite()
824 	hw = clk_hw_register_composite(NULL, clks->name, parent_names,  in bm1880_clk_register_composite()
827 				       clks->flags);  in bm1880_clk_register_composite()
849 	void __iomem *sys_base = data->sys_base;  in bm1880_clk_register_composites()
858 			       __func__, bm1880_clk->name);  in bm1880_clk_register_composites()
862 		data->hw_data.hws[clks[i].id] = hw;  in bm1880_clk_register_composites()
868 	while (i--)  in bm1880_clk_register_composites()
869 		clk_hw_unregister_composite(data->hw_data.hws[clks[i].id]);  in bm1880_clk_register_composites()
878 	struct device *dev = &pdev->dev;  in bm1880_clk_probe()
898 		return -ENOMEM;  in bm1880_clk_probe()
900 	clk_data->pll_base = pll_base;  in bm1880_clk_probe()
901 	clk_data->sys_base = sys_base;  in bm1880_clk_probe()
904 		clk_data->hw_data.hws[i] = ERR_PTR(-ENOENT);  in bm1880_clk_probe()
906 	clk_data->hw_data.num = num_clks;  in bm1880_clk_probe()
929 				      &clk_data->hw_data);  in bm1880_clk_probe()
933 	{ .compatible = "bitmain,bm1880-clk", },
940 		.name = "bm1880-clk",
948 MODULE_DESCRIPTION("Clock driver for Bitmain BM1880 SoC");