Lines Matching +full:power +full:- +full:limits
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright 2012-2013 Analog Devices Inc.
6 * Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/adi-axi-common.h>
12 #include <linux/clk-provider.h>
66 struct axi_clkgen_limits limits;
132 static void axi_clkgen_calc_params(const struct axi_clkgen_limits *limits,
151 d_min = max(DIV_ROUND_UP(fin, limits->fpfd_max), 1);
152 d_max = min(fin / limits->fpfd_min, 80);
155 fvco_min_fract = limits->fvco_min << fract_shift;
156 fvco_max_fract = limits->fvco_max << fract_shift;
171 if (abs(f - fout) < abs(best_f - fout)) {
174 *best_m = m << (3 - fract_shift);
175 *best_dout = dout << (3 - fract_shift);
208 params->nocount = 1;
213 params->high = divider / 2;
214 params->edge = divider % 2;
215 params->low = divider - params->high;
217 params->frac_en = 1;
218 params->frac = frac_divider;
220 params->high = divider / 2;
221 params->edge = divider % 2;
222 params->low = params->high;
224 if (params->edge == 0) {
225 params->high--;
226 params->frac_wf_r = 1;
229 if (params->edge == 0 || frac_divider == 1)
230 params->low--;
231 if (((params->edge == 0) ^ (frac_divider == 1)) ||
233 params->frac_wf_f = 1;
235 params->frac_phase = params->edge * 4 + frac_divider / 2;
242 writel(val, axi_clkgen->base + reg);
248 *val = readl(axi_clkgen->base + reg);
258 } while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);
261 return -EIO;
334 (params->high << 6) | params->low, 0xefff);
336 (params->frac << 12) | (params->frac_en << 11) |
337 (params->frac_wf_r << 10) | (params->edge << 7) |
338 (params->nocount << 6), 0x7fff);
341 (params->frac_phase << 11) | (params->frac_wf_f << 10),
350 const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
353 u32 power = 0, filter, lock;
356 return -EINVAL;
358 axi_clkgen_calc_params(limits, parent_rate, rate, &d, &m, &dout);
361 return -EINVAL;
364 power |= 0x9800;
366 axi_clkgen_mmcm_write(axi_clkgen, MMCM_REG_POWER, power, 0x9800);
368 filter = axi_clkgen_lookup_filter(m - 1);
369 lock = axi_clkgen_lookup_lock(m - 1);
399 const struct axi_clkgen_limits *limits = &axi_clkgen->limits;
403 axi_clkgen_calc_params(limits, req->best_parent_rate, req->rate,
407 return -EINVAL;
409 tmp = (unsigned long long)req->best_parent_rate * m;
412 req->rate = min_t(unsigned long long, tmp, LONG_MAX);
516 axi_clkgen->limits.fpfd_min = 10000;
517 axi_clkgen->limits.fvco_min = 600000;
521 axi_clkgen->limits.fvco_max = 1200000;
522 axi_clkgen->limits.fpfd_max = 450000;
525 axi_clkgen->limits.fvco_max = 1440000;
526 axi_clkgen->limits.fpfd_max = 500000;
531 axi_clkgen->limits.fvco_max = 1200000;
532 axi_clkgen->limits.fpfd_max = 450000;
537 axi_clkgen->limits.fvco_max = 1600000;
538 axi_clkgen->limits.fpfd_max = 550000;
541 return dev_err_probe(dev, -ENODEV, "Unknown speed grade %d\n",
545 /* Overwrite vco limits for ultrascale+ */
547 axi_clkgen->limits.fvco_max = 1600000;
548 axi_clkgen->limits.fvco_min = 800000;
576 dflt_limits = device_get_match_data(&pdev->dev);
578 return -ENODEV;
580 axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
582 return -ENOMEM;
584 axi_clkgen->base = devm_platform_ioremap_resource(pdev, 0);
585 if (IS_ERR(axi_clkgen->base))
586 return PTR_ERR(axi_clkgen->base);
588 init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);
590 axi_clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");
593 return -EINVAL;
595 init.num_parents -= 1;
598 * Legacy... So that old DTs which do not have clock-names still
602 if (PTR_ERR(axi_clk) != -ENOENT)
605 return -EINVAL;
609 parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);
611 return -EINVAL;
617 ret = axi_clkgen_setup_limits(axi_clkgen, &pdev->dev);
621 memcpy(&axi_clkgen->limits, dflt_limits,
622 sizeof(axi_clkgen->limits));
625 clk_name = pdev->dev.of_node->name;
626 of_property_read_string(pdev->dev.of_node, "clock-output-names",
636 axi_clkgen->clk_hw.init = &init;
637 ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);
641 return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,
642 &axi_clkgen->clk_hw);
647 .compatible = "adi,zynqmp-axi-clkgen-2.00.a",
651 .compatible = "adi,axi-clkgen-2.00.a",
660 .name = "adi-axi-clkgen",
668 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");