1 // SPDX-License-Identifier: GPL-2.0-only
5  * Copyright 2012-2013 Analog Devices Inc.
6  *  Author: Lars-Peter Clausen <lars@metafoo.de>
9 #include <linux/adi-axi-common.h>
12 #include <linux/clk-provider.h>
151 	d_min = max(DIV_ROUND_UP(fin, limits->fpfd_max), 1);  in axi_clkgen_calc_params()
152 	d_max = min(fin / limits->fpfd_min, 80);  in axi_clkgen_calc_params()
155 	fvco_min_fract = limits->fvco_min << fract_shift;  in axi_clkgen_calc_params()
156 	fvco_max_fract = limits->fvco_max << fract_shift;  in axi_clkgen_calc_params()
171 			if (abs(f - fout) < abs(best_f - fout)) {  in axi_clkgen_calc_params()
174 				*best_m = m << (3 - fract_shift);  in axi_clkgen_calc_params()
175 				*best_dout = dout << (3 - fract_shift);  in axi_clkgen_calc_params()
190 	unsigned int low;  member
192 	unsigned int edge;  member
208 		params->nocount = 1;  in axi_clkgen_calc_clk_params()
213 		params->high = divider / 2;  in axi_clkgen_calc_clk_params()
214 		params->edge = divider % 2;  in axi_clkgen_calc_clk_params()
215 		params->low = divider - params->high;  in axi_clkgen_calc_clk_params()
217 		params->frac_en = 1;  in axi_clkgen_calc_clk_params()
218 		params->frac = frac_divider;  in axi_clkgen_calc_clk_params()
220 		params->high = divider / 2;  in axi_clkgen_calc_clk_params()
221 		params->edge = divider % 2;  in axi_clkgen_calc_clk_params()
222 		params->low = params->high;  in axi_clkgen_calc_clk_params()
224 		if (params->edge == 0) {  in axi_clkgen_calc_clk_params()
225 			params->high--;  in axi_clkgen_calc_clk_params()
226 			params->frac_wf_r = 1;  in axi_clkgen_calc_clk_params()
229 		if (params->edge == 0 || frac_divider == 1)  in axi_clkgen_calc_clk_params()
230 			params->low--;  in axi_clkgen_calc_clk_params()
231 		if (((params->edge == 0) ^ (frac_divider == 1)) ||  in axi_clkgen_calc_clk_params()
233 			params->frac_wf_f = 1;  in axi_clkgen_calc_clk_params()
235 		params->frac_phase = params->edge * 4 + frac_divider / 2;  in axi_clkgen_calc_clk_params()
242 	writel(val, axi_clkgen->base + reg);  in axi_clkgen_write()
248 	*val = readl(axi_clkgen->base + reg);  in axi_clkgen_read()
258 	} while ((val & AXI_CLKGEN_V2_DRP_STATUS_BUSY) && --timeout);  in axi_clkgen_wait_non_busy()
261 		return -EIO;  in axi_clkgen_wait_non_busy()
334 			      (params->high << 6) | params->low, 0xefff);  in axi_clkgen_set_div()
336 			      (params->frac << 12) | (params->frac_en << 11) |  in axi_clkgen_set_div()
337 			      (params->frac_wf_r << 10) | (params->edge << 7) |  in axi_clkgen_set_div()
338 			      (params->nocount << 6), 0x7fff);  in axi_clkgen_set_div()
341 				      (params->frac_phase << 11) | (params->frac_wf_f << 10),  in axi_clkgen_set_div()
350 	const struct axi_clkgen_limits *limits = &axi_clkgen->limits;  in axi_clkgen_set_rate()
356 		return -EINVAL;  in axi_clkgen_set_rate()
361 		return -EINVAL;  in axi_clkgen_set_rate()
368 	filter = axi_clkgen_lookup_filter(m - 1);  in axi_clkgen_set_rate()
369 	lock = axi_clkgen_lookup_lock(m - 1);  in axi_clkgen_set_rate()
377 			      (params.edge << 13) | (params.nocount << 12) |  in axi_clkgen_set_rate()
378 			      (params.high << 6) | params.low, 0x3fff);  in axi_clkgen_set_rate()
399 	const struct axi_clkgen_limits *limits = &axi_clkgen->limits;  in axi_clkgen_determine_rate()
403 	axi_clkgen_calc_params(limits, req->best_parent_rate, req->rate,  in axi_clkgen_determine_rate()
407 		return -EINVAL;  in axi_clkgen_determine_rate()
409 	tmp = (unsigned long long)req->best_parent_rate * m;  in axi_clkgen_determine_rate()
412 	req->rate = min_t(unsigned long long, tmp, LONG_MAX);  in axi_clkgen_determine_rate()
516 	axi_clkgen->limits.fpfd_min = 10000;  in axi_clkgen_setup_limits()
517 	axi_clkgen->limits.fvco_min = 600000;  in axi_clkgen_setup_limits()
521 		axi_clkgen->limits.fvco_max = 1200000;  in axi_clkgen_setup_limits()
522 		axi_clkgen->limits.fpfd_max = 450000;  in axi_clkgen_setup_limits()
525 		axi_clkgen->limits.fvco_max = 1440000;  in axi_clkgen_setup_limits()
526 		axi_clkgen->limits.fpfd_max = 500000;  in axi_clkgen_setup_limits()
531 				axi_clkgen->limits.fvco_max = 1200000;  in axi_clkgen_setup_limits()
532 				axi_clkgen->limits.fpfd_max = 450000;  in axi_clkgen_setup_limits()
537 		axi_clkgen->limits.fvco_max = 1600000;  in axi_clkgen_setup_limits()
538 		axi_clkgen->limits.fpfd_max = 550000;  in axi_clkgen_setup_limits()
541 		return dev_err_probe(dev, -ENODEV, "Unknown speed grade %d\n",  in axi_clkgen_setup_limits()
547 		axi_clkgen->limits.fvco_max = 1600000;  in axi_clkgen_setup_limits()
548 		axi_clkgen->limits.fvco_min = 800000;  in axi_clkgen_setup_limits()
576 	dflt_limits = device_get_match_data(&pdev->dev);  in axi_clkgen_probe()
578 		return -ENODEV;  in axi_clkgen_probe()
580 	axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);  in axi_clkgen_probe()
582 		return -ENOMEM;  in axi_clkgen_probe()
584 	axi_clkgen->base = devm_platform_ioremap_resource(pdev, 0);  in axi_clkgen_probe()
585 	if (IS_ERR(axi_clkgen->base))  in axi_clkgen_probe()
586 		return PTR_ERR(axi_clkgen->base);  in axi_clkgen_probe()
588 	init.num_parents = of_clk_get_parent_count(pdev->dev.of_node);  in axi_clkgen_probe()
590 	axi_clk = devm_clk_get_enabled(&pdev->dev, "s_axi_aclk");  in axi_clkgen_probe()
593 			return -EINVAL;  in axi_clkgen_probe()
595 		init.num_parents -= 1;  in axi_clkgen_probe()
598 		 * Legacy... So that old DTs which do not have clock-names still  in axi_clkgen_probe()
602 		if (PTR_ERR(axi_clk) != -ENOENT)  in axi_clkgen_probe()
605 			return -EINVAL;  in axi_clkgen_probe()
609 		parent_names[i] = of_clk_get_parent_name(pdev->dev.of_node, i);  in axi_clkgen_probe()
611 			return -EINVAL;  in axi_clkgen_probe()
617 		ret = axi_clkgen_setup_limits(axi_clkgen, &pdev->dev);  in axi_clkgen_probe()
621 		memcpy(&axi_clkgen->limits, dflt_limits,  in axi_clkgen_probe()
622 		       sizeof(axi_clkgen->limits));  in axi_clkgen_probe()
625 	clk_name = pdev->dev.of_node->name;  in axi_clkgen_probe()
626 	of_property_read_string(pdev->dev.of_node, "clock-output-names",  in axi_clkgen_probe()
636 	axi_clkgen->clk_hw.init = &init;  in axi_clkgen_probe()
637 	ret = devm_clk_hw_register(&pdev->dev, &axi_clkgen->clk_hw);  in axi_clkgen_probe()
641 	return devm_of_clk_add_hw_provider(&pdev->dev, of_clk_hw_simple_get,  in axi_clkgen_probe()
642 					   &axi_clkgen->clk_hw);  in axi_clkgen_probe()
647 		.compatible = "adi,zynqmp-axi-clkgen-2.00.a",
651 		.compatible = "adi,axi-clkgen-2.00.a",
660 		.name = "adi-axi-clkgen",
668 MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");