Lines Matching +full:0 +full:x14
33 .aon = AON_VAL(0x0, 1, 15, 12),
34 .reset = RESET_VAL(0x4, 2, 1),
35 .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
36 .ndiv_int = REG_VAL(0x8, 4, 10),
37 .pdiv = REG_VAL(0x8, 0, 4),
38 .vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
39 .status = REG_VAL(0x0, 27, 1),
46 * it to 0.
51 .enable = ENABLE_VAL(0x0, 18, 12, 0),
52 .mdiv = REG_VAL(0x18, 0, 8),
57 .enable = ENABLE_VAL(0x0, 19, 13, 0),
58 .mdiv = REG_VAL(0x18, 8, 8),
63 .enable = ENABLE_VAL(0x0, 20, 14, 0),
64 .mdiv = REG_VAL(0x14, 0, 8),
69 .enable = ENABLE_VAL(0x0, 21, 15, 0),
70 .mdiv = REG_VAL(0x14, 8, 8),
75 .enable = ENABLE_VAL(0x0, 22, 16, 0),
76 .mdiv = REG_VAL(0x14, 16, 8),
81 .enable = ENABLE_VAL(0x0, 23, 17, 0),
82 .mdiv = REG_VAL(0x14, 24, 8),
88 iproc_pll_clk_setup(node, &genpll_scr, NULL, 0, genpll_scr_clk, in ns2_genpll_scr_clk_init()
96 .aon = AON_VAL(0x0, 1, 11, 10),
97 .reset = RESET_VAL(0x4, 2, 1),
98 .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
99 .ndiv_int = REG_VAL(0x8, 4, 10),
100 .pdiv = REG_VAL(0x8, 0, 4),
101 .vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
102 .status = REG_VAL(0x0, 13, 1),
108 * it to 0.
113 .enable = ENABLE_VAL(0x0, 18, 12, 0),
114 .mdiv = REG_VAL(0x18, 0, 8),
119 .enable = ENABLE_VAL(0x0, 19, 13, 0),
120 .mdiv = REG_VAL(0x18, 8, 8),
125 .enable = ENABLE_VAL(0x0, 20, 14, 0),
126 .mdiv = REG_VAL(0x14, 0, 8),
131 .enable = ENABLE_VAL(0x0, 21, 15, 0),
132 .mdiv = REG_VAL(0x14, 8, 8),
137 .enable = ENABLE_VAL(0x0, 22, 16, 0),
138 .mdiv = REG_VAL(0x14, 16, 8),
143 .enable = ENABLE_VAL(0x0, 23, 17, 0),
144 .mdiv = REG_VAL(0x14, 24, 8),
150 iproc_pll_clk_setup(node, &genpll_sw, NULL, 0, genpll_sw_clk, in ns2_genpll_sw_clk_init()
158 .aon = AON_VAL(0x0, 2, 1, 0),
159 .reset = RESET_VAL(0x4, 2, 1),
160 .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 1, 4),
161 .ndiv_int = REG_VAL(0x8, 4, 10),
162 .pdiv = REG_VAL(0x8, 0, 4),
163 .vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
164 .status = REG_VAL(0x0, 0, 1),
170 * it to 0.
175 .enable = ENABLE_VAL(0x0, 18, 12, 0),
176 .mdiv = REG_VAL(0x14, 0, 8),
181 .enable = ENABLE_VAL(0x0, 19, 13, 0),
182 .mdiv = REG_VAL(0x14, 8, 8),
187 .enable = ENABLE_VAL(0x0, 20, 14, 0),
188 .mdiv = REG_VAL(0x10, 0, 8),
193 .enable = ENABLE_VAL(0x0, 21, 15, 0),
194 .mdiv = REG_VAL(0x10, 8, 8),
199 .enable = ENABLE_VAL(0x0, 22, 16, 0),
200 .mdiv = REG_VAL(0x10, 16, 8),
205 .enable = ENABLE_VAL(0x0, 23, 17, 0),
206 .mdiv = REG_VAL(0x10, 24, 8),
212 iproc_pll_clk_setup(node, &lcpll_ddr, NULL, 0, lcpll_ddr_clk, in ns2_lcpll_ddr_clk_init()
220 .aon = AON_VAL(0x0, 2, 5, 4),
221 .reset = RESET_VAL(0x4, 2, 1),
222 .dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 1, 4),
223 .ndiv_int = REG_VAL(0x8, 4, 10),
224 .pdiv = REG_VAL(0x8, 0, 4),
225 .vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
226 .status = REG_VAL(0x0, 0, 1),
232 * it to 0.
237 .enable = ENABLE_VAL(0x0, 18, 12, 0),
238 .mdiv = REG_VAL(0x14, 0, 8),
243 .enable = ENABLE_VAL(0x0, 19, 13, 0),
244 .mdiv = REG_VAL(0x14, 8, 8),
249 .enable = ENABLE_VAL(0x0, 20, 14, 0),
250 .mdiv = REG_VAL(0x10, 0, 8),
255 .enable = ENABLE_VAL(0x0, 21, 15, 0),
256 .mdiv = REG_VAL(0x10, 8, 8),
261 .enable = ENABLE_VAL(0x0, 22, 16, 0),
262 .mdiv = REG_VAL(0x10, 16, 8),
267 .enable = ENABLE_VAL(0x0, 23, 17, 0),
268 .mdiv = REG_VAL(0x10, 24, 8),
274 iproc_pll_clk_setup(node, &lcpll_ports, NULL, 0, lcpll_ports_clk, in ns2_lcpll_ports_clk_init()