Lines Matching +full:trigger +full:- +full:value
1 /* SPDX-License-Identifier: GPL-2.0-only */
16 #include <linux/clk-provider.h>
24 #define BAD_CLK_NAME ((const char *)-1)
30 * should be defined such that 0 is the desired default value.
33 #define FLAG_SET(obj, type, flag) ((obj)->flags |= FLAG(type, flag))
34 #define FLAG_CLEAR(obj, type, flag) ((obj)->flags &= ~(FLAG(type, flag)))
35 #define FLAG_FLIP(obj, type, flag) ((obj)->flags ^= FLAG(type, flag))
36 #define FLAG_TEST(obj, type, flag) (!!((obj)->flags & FLAG(type, flag)))
40 #define ccu_policy_exists(ccu_policy) ((ccu_policy)->enable.offset != 0)
44 #define policy_exists(policy) ((policy)->offset != 0)
55 #define hyst_exists(hyst) ((hyst)->offset != 0)
60 (div)->u.s.frac_width > 0)
62 #define selector_exists(sel) ((sel)->width != 0)
65 #define policy_lvm_en_exists(enable) ((enable)->offset != 0)
66 #define policy_ctl_exists(control) ((control)->offset != 0)
98 * Gating control and status is managed by a 32-bit gate register.
101 * - (no gate)
103 * - hardware-only gating (auto-gating)
107 * of auto-gated clocks can be read from the gate status bit.
108 * - software-only gating
109 * Auto-gating is not available for this type of clock.
116 * - selectable hardware or software gating
131 * HW means this gate can be auto-gated
135 * ENABLED means this software-managed gate is *supposed* to be enabled
138 #define BCM_CLK_GATE_FLAGS_HW ((u32)1 << 1) /* Can auto-gate */
173 /* A hardware-or-enabled gate (enabled if not under hardware control) */
184 /* A software-only gate */
194 /* A hardware-only gate */
221 * variable. If there are two dividers, they are the "pre-divider"
223 * there is no pre-divider.
225 * A fixed divider is any non-zero (positive) value, and it
228 * The value of a variable divider is maintained in a sub-field of a
229 * 32-bit divider register. The position of the field in the
230 * register is defined by its offset and width. The value recorded
231 * in this field is always 1 less than the value it represents.
235 * bits comprise the low-order portion of the divider field, and can
238 * fractional bits. Variable dividers with non-zero fraction width
239 * still record a value 1 less than the value they represent; the
240 * added 1 does *not* affect the low-order bit in this case, it
242 * code a divider field value is distinguished from the value it
246 * performed using "scaled" values. A scaled value is one that's
247 * been left-shifted by the fractional width of a divider. Dividing
248 * a scaled value by a scaled divisor produces the desired quotient
252 * The recorded value of a variable divider can be modified. To
254 * using its gate). In addition, a trigger register (described
266 u64 scaled_div; /* scaled divider value */
268 u32 fixed; /* non-zero fixed divider value */
276 * FIXED means it is a fixed-rate divider
279 #define BCM_CLK_DIV_FLAGS_FIXED ((u32)1 << 1) /* Fixed-value */
283 /* A fixed (non-zero) divider */
315 * sub-field of a 32-bit selector register. The range of
317 * available parent clocks. Occasionally the reset value of a
318 * selector field is explicitly set to a (specific) value that does
329 * must be enabled, and a trigger must be used to commit the change.
352 * requires the use of a trigger. A trigger is defined by a single
355 * trigger bit is polled; the read value will be 1 while the change
358 * Occasionally a clock will have more than one trigger. In this
359 * case, the "pre-trigger" will be used when changing a clock's
360 * selector and/or its pre-divider.
363 u32 offset; /* trigger register offset */
364 u32 bit; /* trigger bit */
369 * Trigger flags:
370 * EXISTS means this trigger exists
372 #define BCM_CLK_TRIG_FLAGS_EXISTS ((u32)1 << 0) /* Trigger is valid */
374 /* Trigger initialization macro */
375 #define TRIGGER(_offset, _bit) \ macro
465 * (other) address can be written, a special access "password" value