46 #define gate_exists(gate)		FLAG_TEST(gate, GATE, EXISTS)  argument
47 #define gate_is_enabled(gate)		FLAG_TEST(gate, GATE, ENABLED)  argument
48 #define gate_is_hw_controllable(gate)	FLAG_TEST(gate, GATE, HW)  argument
49 #define gate_is_sw_controllable(gate)	FLAG_TEST(gate, GATE, SW)  argument
50 #define gate_is_sw_managed(gate)	FLAG_TEST(gate, GATE, SW_MANAGED)  argument
51 #define gate_is_no_disable(gate)	FLAG_TEST(gate, GATE, NO_DISABLE)  argument
53 #define gate_flip_enabled(gate)		FLAG_FLIP(gate, GATE, ENABLED)  argument
98  * Gating control and status is managed by a 32-bit gate register.
101  * - (no gate)
102  *     A clock with no gate is assumed to be always enabled.
104  *     Enabling or disabling clocks with this type of gate is
107  *     of auto-gated clocks can be read from the gate status bit.
111  *     clearing the enable bit.  The current gate status of a gate
112  *     under software control can be read from the gate status bit.
114  *     status bit can be polled to verify that the gate has entered
119  *     determined by the hw_sw_sel bit of the gate register.
122 	u32 offset;		/* gate register offset */
123 	u32 status_bit;		/* 0: gate is disabled; 0: gatge is enabled */
130  * Gate flags:
131  *   HW         means this gate can be auto-gated
132  *   SW         means the state of this gate can be software controlled
133  *   NO_DISABLE means this gate is (only) enabled if under software control
134  *   SW_MANAGED means the status of this gate is under software control
135  *   ENABLED    means this software-managed gate is *supposed* to be enabled
137 #define BCM_CLK_GATE_FLAGS_EXISTS	((u32)1 << 0)	/* Gate is valid */
138 #define BCM_CLK_GATE_FLAGS_HW		((u32)1 << 1)	/* Can auto-gate */
145  * Gate initialization macros.
147  * Any gate initially under software control will be enabled.
150 /* A hardware/software gate initially under software control */
157 		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
158 			FLAG(GATE, SW_MANAGED)|FLAG(GATE, ENABLED)|	\
159 			FLAG(GATE, EXISTS),				\
162 /* A hardware/software gate initially under hardware control */
169 		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
170 			FLAG(GATE, EXISTS),				\
173 /* A hardware-or-enabled gate (enabled if not under hardware control) */
180 		.flags = FLAG(GATE, HW)|FLAG(GATE, SW)|			\
181 			FLAG(GATE, NO_DISABLE)|FLAG(GATE, EXISTS),	\
184 /* A software-only gate */
190 		.flags = FLAG(GATE, SW)|FLAG(GATE, SW_MANAGED)|		\
191 			FLAG(GATE, ENABLED)|FLAG(GATE, EXISTS),		\
194 /* A hardware-only gate */
199 		.flags = FLAG(GATE, HW)|FLAG(GATE, EXISTS),		\
202 /* Gate hysteresis for clocks */
254  * using its gate).  In addition, a trigger register (described
384 	struct bcm_clk_gate gate;  member