1 // SPDX-License-Identifier: GPL-2.0-only
7 #include "clk-kona.h"
12 #include <linux/clk-provider.h>
28 /* Produces a mask of set bits covering a range of a 32-bit value */
31 	return ((1 << width) - 1) << shift;  in bitfield_mask()
51 static inline u64 scaled_div_value(struct bcm_clk_div *div, u32 reg_div)  in scaled_div_value()  argument
53 	return (u64)reg_div + ((u64)1 << div->u.s.frac_width);  in scaled_div_value()
58 scaled_div_min(struct bcm_clk_div *div)  in scaled_div_min()  argument
60 	if (divider_is_fixed(div))  in scaled_div_min()
61 		return (u64)div->u.fixed;  in scaled_div_min()
63 	return scaled_div_value(div, 0);  in scaled_div_min()
67 u64 scaled_div_max(struct bcm_clk_div *div)  in scaled_div_max()  argument
71 	if (divider_is_fixed(div))  in scaled_div_max()
72 		return (u64)div->u.fixed;  in scaled_div_max()
74 	reg_div = ((u32)1 << div->u.s.width) - 1;  in scaled_div_max()
76 	return scaled_div_value(div, reg_div);  in scaled_div_max()
84 divider(struct bcm_clk_div *div, u64 scaled_div)  in divider()  argument
86 	BUG_ON(scaled_div < scaled_div_min(div));  in divider()
87 	BUG_ON(scaled_div > scaled_div_max(div));  in divider()
89 	return (u32)(scaled_div - ((u64)1 << div->u.s.frac_width));  in divider()
94 scale_rate(struct bcm_clk_div *div, u32 rate)  in scale_rate()  argument
96 	if (divider_is_fixed(div))  in scale_rate()
99 	return (u64)rate << div->u.s.frac_width;  in scale_rate()
104 /* Read a 32-bit register value from a CCU's address space. */
107 	return readl(ccu->base + reg_offset);  in __ccu_read()
110 /* Write a 32-bit register value into a CCU's address space. */
114 	writel(reg_val, ccu->base + reg_offset);  in __ccu_write()
121 	spin_lock_irqsave(&ccu->lock, flags);  in ccu_lock()
127 	spin_unlock_irqrestore(&ccu->lock, flags);  in ccu_unlock()
136 	if (ccu->write_enabled) {  in __ccu_write_enable()
138 			ccu->name);  in __ccu_write_enable()
141 	ccu->write_enabled = true;  in __ccu_write_enable()
147 	if (!ccu->write_enabled) {  in __ccu_write_disable()
149 			ccu->name);  in __ccu_write_disable()
154 	ccu->write_enabled = false;  in __ccu_write_disable()
182 		ccu->name, reg_offset, bit, want ? "set" : "clear");  in __ccu_wait_bit()
191 	struct bcm_policy_ctl *control = &ccu->policy.control;  in __ccu_policy_engine_start()
201 	offset = control->offset;  in __ccu_policy_engine_start()
202 	go_bit = control->go_bit;  in __ccu_policy_engine_start()
208 			__func__, ccu->name);  in __ccu_policy_engine_start()
222 	 * (ATL bit clear) and setting the request auto-copy (AC bit  in __ccu_policy_engine_start()
225 	 * Note, we do NOT read-modify-write this register.  in __ccu_policy_engine_start()
229 		mask |= 1 << control->atl_bit;  in __ccu_policy_engine_start()
231 		mask |= 1 << control->ac_bit;  in __ccu_policy_engine_start()
238 			__func__, ccu->name);  in __ccu_policy_engine_start()
245 	struct bcm_lvm_en *enable = &ccu->policy.enable;  in __ccu_policy_engine_stop()
255 	offset = enable->offset;  in __ccu_policy_engine_stop()
256 	enable_bit = enable->bit;  in __ccu_policy_engine_stop()
260 			__func__, ccu->name);  in __ccu_policy_engine_stop()
264 	/* Now set the bit to stop the engine (NO read-modify-write) */  in __ccu_policy_engine_stop()
271 			__func__, ccu->name);  in __ccu_policy_engine_stop()
280  * each policy indicating whether the clock is enabled for that
281  * policy or not.  The bit position for a clock is the same for all
282  * four registers, and the 32-bit registers are at consecutive
301 			__func__, ccu->name);  in policy_init()
306 	 * For now, if a clock defines its policy bit we just mark  in policy_init()
309 	offset = policy->offset;  in policy_init()
310 	mask = (u32)1 << policy->bit;  in policy_init()
324 			__func__, ccu->name);  in policy_init()
331 /* Determine whether a clock is gated.  CCU lock must be held.  */
342 	bit_mask = 1 << gate->status_bit;  in __is_clk_gate_enabled()
343 	reg_val = __ccu_read(ccu, gate->offset);  in __is_clk_gate_enabled()
348 /* Determine whether a clock is gated. */
381 	reg_val = __ccu_read(ccu, gate->offset);  in __gate_commit()
385 		mask = (u32)1 << gate->hw_sw_sel_bit;  in __gate_commit()
399 	mask = (u32)1 << gate->en_bit;  in __gate_commit()
406 	__ccu_write(ccu, gate->offset, reg_val);  in __gate_commit()
413 	return __ccu_wait_bit(ccu, gate->offset, gate->status_bit, enabled);  in __gate_commit()
460 /* Enable or disable a gate.  Returns 0 if successful, -EIO otherwise */
490 	return -EIO;  in clk_gate()
496  * If a clock gate requires a turn-off delay it will have
500  * defined for a clock, we set it.
511 	offset = hyst->offset;  in hyst_init()
512 	mask = (u32)1 << hyst->en_bit;  in hyst_init()
513 	mask |= (u32)1 << hyst->val_bit;  in hyst_init()
530 	/* Trigger the clock and wait for it to finish */  in __clk_trigger()
531 	__ccu_write(ccu, trig->offset, 1 << trig->bit);  in __clk_trigger()
533 	return __ccu_wait_bit(ccu, trig->offset, trig->bit, false);  in __clk_trigger()
539 static u64 divider_read_scaled(struct ccu_data *ccu, struct bcm_clk_div *div)  in divider_read_scaled()  argument
545 	if (divider_is_fixed(div))  in divider_read_scaled()
546 		return (u64)div->u.fixed;  in divider_read_scaled()
549 	reg_val = __ccu_read(ccu, div->u.s.offset);  in divider_read_scaled()
553 	reg_div = bitfield_extract(reg_val, div->u.s.shift, div->u.s.width);  in divider_read_scaled()
556 	return scaled_div_value(div, reg_div);  in divider_read_scaled()
563  * Returns 0 on success.  Returns -EINVAL for invalid arguments.
564  * Returns -ENXIO if gating failed, and -EIO if a trigger failed.
567 			struct bcm_clk_div *div, struct bcm_clk_trig *trig)  in __div_commit()  argument
574 	BUG_ON(divider_is_fixed(div));  in __div_commit()
581 	if (div->u.s.scaled_div == BAD_SCALED_DIV_VALUE) {  in __div_commit()
582 		reg_val = __ccu_read(ccu, div->u.s.offset);  in __div_commit()
583 		reg_div = bitfield_extract(reg_val, div->u.s.shift,  in __div_commit()
584 						div->u.s.width);  in __div_commit()
585 		div->u.s.scaled_div = scaled_div_value(div, reg_div);  in __div_commit()
591 	reg_div = divider(div, div->u.s.scaled_div);  in __div_commit()
593 	/* Clock needs to be enabled before changing the rate */  in __div_commit()
596 		ret = -ENXIO;  in __div_commit()
601 	reg_val = __ccu_read(ccu, div->u.s.offset);  in __div_commit()
602 	reg_val = bitfield_replace(reg_val, div->u.s.shift, div->u.s.width,  in __div_commit()
604 	__ccu_write(ccu, div->u.s.offset, reg_val);  in __div_commit()
608 		ret = -EIO;  in __div_commit()
610 	/* Disable the clock again if it was disabled to begin with */  in __div_commit()
612 		ret = ret ? ret : -ENXIO;	/* return first error */  in __div_commit()
623 			struct bcm_clk_div *div, struct bcm_clk_trig *trig)  in div_init()  argument
625 	if (!divider_exists(div) || divider_is_fixed(div))  in div_init()
627 	return !__div_commit(ccu, gate, div, trig);  in div_init()
631 			struct bcm_clk_div *div, struct bcm_clk_trig *trig,  in divider_write()  argument
638 	BUG_ON(divider_is_fixed(div));  in divider_write()
640 	previous = div->u.s.scaled_div;  in divider_write()
644 	div->u.s.scaled_div = scaled_div;  in divider_write()
649 	ret = __div_commit(ccu, gate, div, trig);  in divider_write()
655 		div->u.s.scaled_div = previous;		/* Revert the change */  in divider_write()
661 /* Common clock rate helpers */
664  * Implement the common clock framework recalc_rate method, taking
665  * into account a divider and an optional pre-divider.  The
666  * pre-divider register pointer may be NULL.
669 			struct bcm_clk_div *div, struct bcm_clk_div *pre_div,  in clk_recalc_rate()  argument
676 	if (!divider_exists(div))  in clk_recalc_rate()
683 	 * If there is a pre-divider, divide the scaled parent rate  in clk_recalc_rate()
684 	 * by the pre-divider value first.  In this case--to improve  in clk_recalc_rate()
685 	 * accuracy--scale the parent rate by *both* the pre-divider  in clk_recalc_rate()
687 	 * result of the pre-divider.  in clk_recalc_rate()
695 		scaled_rate = scale_rate(div, scaled_rate);  in clk_recalc_rate()
700 		scaled_parent_rate = scale_rate(div, parent_rate);  in clk_recalc_rate()
705 	 * parent rate by that to determine this clock's resulting  in clk_recalc_rate()
708 	scaled_div = divider_read_scaled(ccu, div);  in clk_recalc_rate()
716  * into two dividers.  The pre-divider can be NULL, and even if it's
717  * non-null it may be nonexistent.  It's also OK for the divider to
718  * be nonexistent, and in that case the pre-divider is also ignored.
720  * If scaled_div is non-null, it is used to return the scaled divisor
723 static long round_rate(struct ccu_data *ccu, struct bcm_clk_div *div,  in round_rate()  argument
734 	BUG_ON(!divider_exists(div));  in round_rate()
739 	 * If there is a pre-divider, divide the scaled parent rate  in round_rate()
740 	 * by the pre-divider value first.  In this case--to improve  in round_rate()
741 	 * accuracy--scale the parent rate by *both* the pre-divider  in round_rate()
743 	 * result of the pre-divider.  in round_rate()
747 	 * For simplicity we treat the pre-divider as fixed (for now).  in round_rate()
754 		scaled_rate = scale_rate(div, scaled_rate);  in round_rate()
759 		scaled_parent_rate = scale_rate(div, parent_rate);  in round_rate()
767 	if (!divider_is_fixed(div)) {  in round_rate()
770 		min_scaled_div = scaled_div_min(div);  in round_rate()
771 		max_scaled_div = scaled_div_max(div);  in round_rate()
777 		best_scaled_div = divider_read_scaled(ccu, div);  in round_rate()
789 /* Common clock parent helpers */
800 	BUG_ON(sel->parent_count > (u32)U8_MAX);  in parent_index()
801 	for (i = 0; i < sel->parent_count; i++)  in parent_index()
802 		if (sel->parent_sel[i] == parent_sel)  in parent_index()
810  * the clock framework.
828 	reg_val = __ccu_read(ccu, sel->offset);  in selector_read_index()
831 	parent_sel = bitfield_extract(reg_val, sel->shift, sel->width);  in selector_read_index()
836 		pr_err("%s: out-of-range parent selector %u (%s 0x%04x)\n",  in selector_read_index()
837 			__func__, parent_sel, ccu->name, sel->offset);  in selector_read_index()
845  * Returns 0 on success.  Returns -EINVAL for invalid arguments.
846  * Returns -ENXIO if gating failed, and -EIO if a trigger failed.
864 	if (sel->clk_index == BAD_CLK_INDEX) {  in __sel_commit()
867 		reg_val = __ccu_read(ccu, sel->offset);  in __sel_commit()
868 		parent_sel = bitfield_extract(reg_val, sel->shift, sel->width);  in __sel_commit()
871 			return -EINVAL;  in __sel_commit()
872 		sel->clk_index = index;  in __sel_commit()
877 	BUG_ON((u32)sel->clk_index >= sel->parent_count);  in __sel_commit()
878 	parent_sel = sel->parent_sel[sel->clk_index];  in __sel_commit()
880 	/* Clock needs to be enabled before changing the parent */  in __sel_commit()
883 		return -ENXIO;  in __sel_commit()
886 	reg_val = __ccu_read(ccu, sel->offset);  in __sel_commit()
887 	reg_val = bitfield_replace(reg_val, sel->shift, sel->width, parent_sel);  in __sel_commit()
888 	__ccu_write(ccu, sel->offset, reg_val);  in __sel_commit()
892 		ret = -EIO;  in __sel_commit()
894 	/* Disable the clock again if it was disabled to begin with */  in __sel_commit()
896 		ret = ret ? ret : -ENXIO;	/* return first error */  in __sel_commit()
916  * different parent clock.  Returns 0 on success, or an error code
927 	previous = sel->clk_index;  in selector_write()
931 	sel->clk_index = index;  in selector_write()
942 		sel->clk_index = previous;	/* Revert the change */  in selector_write()
947 /* Clock operations */
952 	struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate;  in kona_peri_clk_enable()
954 	return clk_gate(bcm_clk->ccu, bcm_clk->init_data.name, gate, true);  in kona_peri_clk_enable()
960 	struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate;  in kona_peri_clk_disable()
962 	(void)clk_gate(bcm_clk->ccu, bcm_clk->init_data.name, gate, false);  in kona_peri_clk_disable()
968 	struct bcm_clk_gate *gate = &bcm_clk->u.peri->gate;  in kona_peri_clk_is_enabled()
970 	return is_clk_gate_enabled(bcm_clk->ccu, gate) ? 1 : 0;  in kona_peri_clk_is_enabled()
977 	struct peri_clk_data *data = bcm_clk->u.peri;  in kona_peri_clk_recalc_rate()
979 	return clk_recalc_rate(bcm_clk->ccu, &data->div, &data->pre_div,  in kona_peri_clk_recalc_rate()
987 	struct bcm_clk_div *div = &bcm_clk->u.peri->div;  in kona_peri_clk_round_rate()  local
989 	if (!divider_exists(div))  in kona_peri_clk_round_rate()
993 	return round_rate(bcm_clk->ccu, div, &bcm_clk->u.peri->pre_div,  in kona_peri_clk_round_rate()
1013 	WARN_ON_ONCE(bcm_clk->init_data.flags & CLK_SET_RATE_NO_REPARENT);  in kona_peri_clk_determine_rate()
1014 	parent_count = (u32)bcm_clk->init_data.num_parents;  in kona_peri_clk_determine_rate()
1016 		rate = kona_peri_clk_round_rate(hw, req->rate,  in kona_peri_clk_determine_rate()
1017 						&req->best_parent_rate);  in kona_peri_clk_determine_rate()
1021 		req->rate = rate;  in kona_peri_clk_determine_rate()
1028 	best_rate = kona_peri_clk_round_rate(hw, req->rate, &parent_rate);  in kona_peri_clk_determine_rate()
1029 	best_delta = abs(best_rate - req->rate);  in kona_peri_clk_determine_rate()
1031 	/* Check whether any other parent clock can produce a better result */  in kona_peri_clk_determine_rate()
1043 		other_rate = kona_peri_clk_round_rate(hw, req->rate,  in kona_peri_clk_determine_rate()
1045 		delta = abs(other_rate - req->rate);  in kona_peri_clk_determine_rate()
1049 			req->best_parent_hw = parent;  in kona_peri_clk_determine_rate()
1050 			req->best_parent_rate = parent_rate;  in kona_peri_clk_determine_rate()
1054 	req->rate = best_rate;  in kona_peri_clk_determine_rate()
1061 	struct peri_clk_data *data = bcm_clk->u.peri;  in kona_peri_clk_set_parent()
1062 	struct bcm_clk_sel *sel = &data->sel;  in kona_peri_clk_set_parent()
1066 	BUG_ON(index >= sel->parent_count);  in kona_peri_clk_set_parent()
1074 	 * pre-trigger we want to use that instead.  in kona_peri_clk_set_parent()
1076 	trig = trigger_exists(&data->pre_trig) ? &data->pre_trig  in kona_peri_clk_set_parent()
1077 					       : &data->trig;  in kona_peri_clk_set_parent()
1079 	ret = selector_write(bcm_clk->ccu, &data->gate, sel, trig, index);  in kona_peri_clk_set_parent()
1080 	if (ret == -ENXIO) {  in kona_peri_clk_set_parent()
1082 			bcm_clk->init_data.name);  in kona_peri_clk_set_parent()
1083 		ret = -EIO;	/* Don't proliferate weird errors */  in kona_peri_clk_set_parent()
1084 	} else if (ret == -EIO) {  in kona_peri_clk_set_parent()
1086 			trig == &data->pre_trig ? "pre-" : "",  in kona_peri_clk_set_parent()
1087 			bcm_clk->init_data.name);  in kona_peri_clk_set_parent()
1096 	struct peri_clk_data *data = bcm_clk->u.peri;  in kona_peri_clk_get_parent()
1099 	index = selector_read_index(bcm_clk->ccu, &data->sel);  in kona_peri_clk_get_parent()
1101 	/* Not all callers would handle an out-of-range value gracefully */  in kona_peri_clk_get_parent()
1109 	struct peri_clk_data *data = bcm_clk->u.peri;  in kona_peri_clk_set_rate()
1110 	struct bcm_clk_div *div = &data->div;  in kona_peri_clk_set_rate()  local
1115 		return -EINVAL;  in kona_peri_clk_set_rate()
1120 	if (!divider_exists(div))  in kona_peri_clk_set_rate()
1121 		return rate == parent_rate ? 0 : -EINVAL;  in kona_peri_clk_set_rate()
1125 	 * pre-divider be, but for now we never actually try to  in kona_peri_clk_set_rate()
1126 	 * change that.)  Tolerate a request for a no-op change.  in kona_peri_clk_set_rate()
1128 	if (divider_is_fixed(&data->div))  in kona_peri_clk_set_rate()
1129 		return rate == parent_rate ? 0 : -EINVAL;  in kona_peri_clk_set_rate()
1132 	 * Get the scaled divisor value needed to achieve a clock  in kona_peri_clk_set_rate()
1134 	 * the parent clock rate supplied.  in kona_peri_clk_set_rate()
1136 	(void)round_rate(bcm_clk->ccu, div, &data->pre_div,  in kona_peri_clk_set_rate()
1140 	 * We aren't updating any pre-divider at this point, so  in kona_peri_clk_set_rate()
1143 	ret = divider_write(bcm_clk->ccu, &data->gate, &data->div,  in kona_peri_clk_set_rate()
1144 				&data->trig, scaled_div);  in kona_peri_clk_set_rate()
1145 	if (ret == -ENXIO) {  in kona_peri_clk_set_rate()
1147 			bcm_clk->init_data.name);  in kona_peri_clk_set_rate()
1148 		ret = -EIO;	/* Don't proliferate weird errors */  in kona_peri_clk_set_rate()
1149 	} else if (ret == -EIO) {  in kona_peri_clk_set_rate()
1151 			bcm_clk->init_data.name);  in kona_peri_clk_set_rate()
1168 /* Put a peripheral clock into its initial state */
1171 	struct ccu_data *ccu = bcm_clk->ccu;  in __peri_clk_init()
1172 	struct peri_clk_data *peri = bcm_clk->u.peri;  in __peri_clk_init()
1173 	const char *name = bcm_clk->init_data.name;  in __peri_clk_init()
1176 	BUG_ON(bcm_clk->type != bcm_clk_peri);  in __peri_clk_init()
1178 	if (!policy_init(ccu, &peri->policy)) {  in __peri_clk_init()
1183 	if (!gate_init(ccu, &peri->gate)) {  in __peri_clk_init()
1187 	if (!hyst_init(ccu, &peri->hyst)) {  in __peri_clk_init()
1191 	if (!div_init(ccu, &peri->gate, &peri->div, &peri->trig)) {  in __peri_clk_init()
1198 	 * For the pre-divider and selector, the pre-trigger is used  in __peri_clk_init()
1201 	trig = trigger_exists(&peri->pre_trig) ? &peri->pre_trig  in __peri_clk_init()
1202 					       : &peri->trig;  in __peri_clk_init()
1204 	if (!div_init(ccu, &peri->gate, &peri->pre_div, trig)) {  in __peri_clk_init()
1205 		pr_err("%s: error initializing pre-divider for %s\n", __func__,  in __peri_clk_init()
1210 	if (!sel_init(ccu, &peri->gate, &peri->sel, trig)) {  in __peri_clk_init()
1221 	switch (bcm_clk->type) {  in __kona_clk_init()
1235 	struct kona_clk *kona_clks = ccu->kona_clks;  in kona_ccu_init()
1241 	for (which = 0; which < ccu->clk_num; which++) {  in kona_ccu_init()
1244 		if (!bcm_clk->ccu)  in kona_ccu_init()