Lines Matching +full:8 +full:- +full:channel

1 // SPDX-License-Identifier: GPL-2.0-only
6 #include <linux/clk-provider.h>
13 #include <dt-bindings/clock/bcm-cygnus.h>
14 #include "clk-iproc.h"
45 CLK_OF_DECLARE(cygnus_armpll, "brcm,cygnus-armpll", cygnus_armpll_init);
63 .channel = BCM_CYGNUS_GENPLL_AXI21_CLK,
66 .mdiv = REG_VAL(0x20, 0, 8),
69 .channel = BCM_CYGNUS_GENPLL_250MHZ_CLK,
72 .mdiv = REG_VAL(0x20, 10, 8),
75 .channel = BCM_CYGNUS_GENPLL_IHOST_SYS_CLK,
77 .enable = ENABLE_VAL(0x4, 8, 2, 14),
78 .mdiv = REG_VAL(0x20, 20, 8),
81 .channel = BCM_CYGNUS_GENPLL_ENET_SW_CLK,
84 .mdiv = REG_VAL(0x24, 0, 8),
87 .channel = BCM_CYGNUS_GENPLL_AUDIO_125_CLK,
90 .mdiv = REG_VAL(0x24, 10, 8),
93 .channel = BCM_CYGNUS_GENPLL_CAN_CLK,
96 .mdiv = REG_VAL(0x24, 20, 8),
105 CLK_OF_DECLARE(cygnus_genpll, "brcm,cygnus-genpll", cygnus_genpll_clk_init);
121 .channel = BCM_CYGNUS_LCPLL0_PCIE_PHY_REF_CLK,
124 .mdiv = REG_VAL(0x8, 0, 8),
127 .channel = BCM_CYGNUS_LCPLL0_DDR_PHY_CLK,
129 .enable = ENABLE_VAL(0x0, 8, 2, 14),
130 .mdiv = REG_VAL(0x8, 10, 8),
133 .channel = BCM_CYGNUS_LCPLL0_SDIO_CLK,
136 .mdiv = REG_VAL(0x8, 20, 8),
139 .channel = BCM_CYGNUS_LCPLL0_USB_PHY_REF_CLK,
142 .mdiv = REG_VAL(0xc, 0, 8),
145 .channel = BCM_CYGNUS_LCPLL0_SMART_CARD_CLK,
148 .mdiv = REG_VAL(0xc, 10, 8),
151 .channel = BCM_CYGNUS_LCPLL0_CH5_UNUSED,
154 .mdiv = REG_VAL(0xc, 20, 8),
163 CLK_OF_DECLARE(cygnus_lcpll0, "brcm,cygnus-lcpll0", cygnus_lcpll0_clk_init);
199 .channel = BCM_CYGNUS_MIPIPLL_CH0_UNUSED,
202 .mdiv = REG_VAL(0x20, 0, 8),
205 .channel = BCM_CYGNUS_MIPIPLL_CH1_LCD,
208 .mdiv = REG_VAL(0x20, 10, 8),
211 .channel = BCM_CYGNUS_MIPIPLL_CH2_V3D,
213 .enable = ENABLE_VAL(0x4, 14, 8, 20),
214 .mdiv = REG_VAL(0x20, 20, 8),
217 .channel = BCM_CYGNUS_MIPIPLL_CH3_UNUSED,
220 .mdiv = REG_VAL(0x24, 0, 8),
223 .channel = BCM_CYGNUS_MIPIPLL_CH4_UNUSED,
226 .mdiv = REG_VAL(0x24, 10, 8),
229 .channel = BCM_CYGNUS_MIPIPLL_CH5_UNUSED,
232 .mdiv = REG_VAL(0x24, 20, 8),
242 CLK_OF_DECLARE(cygnus_mipipll, "brcm,cygnus-mipipll", cygnus_mipipll_clk_init);
260 CLK_OF_DECLARE(cygnus_asiu_clk, "brcm,cygnus-asiu-clk", cygnus_asiu_init);
279 .channel = BCM_CYGNUS_AUDIOPLL_CH0,
281 .enable = ENABLE_VAL(0x14, 8, 10, 9),
282 .mdiv = REG_VAL(0x14, 0, 8),
285 .channel = BCM_CYGNUS_AUDIOPLL_CH1,
287 .enable = ENABLE_VAL(0x18, 8, 10, 9),
288 .mdiv = REG_VAL(0x18, 0, 8),
291 .channel = BCM_CYGNUS_AUDIOPLL_CH2,
293 .enable = ENABLE_VAL(0x1c, 8, 10, 9),
294 .mdiv = REG_VAL(0x1c, 0, 8),
303 CLK_OF_DECLARE(cygnus_audiopll, "brcm,cygnus-audiopll",