Lines Matching +full:12 +full:bit +full:- +full:clk +full:- +full:divider
1 // SPDX-License-Identifier: GPL-2.0+
27 #include <linux/clk-provider.h>
29 #include <linux/clk.h>
38 #include <dt-bindings/clock/bcm2835.h>
44 # define CM_DIV_FRAC_BITS 12
45 # define CM_DIV_FRAC_MASK GENMASK(CM_DIV_FRAC_BITS - 1, 0)
93 # define CM_TCNT_SRC1_SHIFT 12
122 # define CM_ENABLE BIT(4)
123 # define CM_KILL BIT(5)
125 # define CM_GATE BIT(CM_GATE_BIT)
126 # define CM_BUSY BIT(7)
127 # define CM_BUSYD BIT(8)
128 # define CM_FRAC BIT(9)
150 # define CM_PLL_ANARST BIT(8)
151 # define CM_PLLA_HOLDPER BIT(7)
152 # define CM_PLLA_LOADPER BIT(6)
153 # define CM_PLLA_HOLDCORE BIT(5)
154 # define CM_PLLA_LOADCORE BIT(4)
155 # define CM_PLLA_HOLDCCP2 BIT(3)
156 # define CM_PLLA_LOADCCP2 BIT(2)
157 # define CM_PLLA_HOLDDSI0 BIT(1)
158 # define CM_PLLA_LOADDSI0 BIT(0)
161 # define CM_PLLC_HOLDPER BIT(7)
162 # define CM_PLLC_LOADPER BIT(6)
163 # define CM_PLLC_HOLDCORE2 BIT(5)
164 # define CM_PLLC_LOADCORE2 BIT(4)
165 # define CM_PLLC_HOLDCORE1 BIT(3)
166 # define CM_PLLC_LOADCORE1 BIT(2)
167 # define CM_PLLC_HOLDCORE0 BIT(1)
168 # define CM_PLLC_LOADCORE0 BIT(0)
171 # define CM_PLLD_HOLDPER BIT(7)
172 # define CM_PLLD_LOADPER BIT(6)
173 # define CM_PLLD_HOLDCORE BIT(5)
174 # define CM_PLLD_LOADCORE BIT(4)
175 # define CM_PLLD_HOLDDSI1 BIT(3)
176 # define CM_PLLD_LOADDSI1 BIT(2)
177 # define CM_PLLD_HOLDDSI0 BIT(1)
178 # define CM_PLLD_LOADDSI0 BIT(0)
181 # define CM_PLLH_LOADRCAL BIT(2)
182 # define CM_PLLH_LOADAUX BIT(1)
183 # define CM_PLLH_LOADPIX BIT(0)
186 # define CM_LOCK_FLOCKH BIT(12)
187 # define CM_LOCK_FLOCKD BIT(11)
188 # define CM_LOCK_FLOCKC BIT(10)
189 # define CM_LOCK_FLOCKB BIT(9)
190 # define CM_LOCK_FLOCKA BIT(8)
201 # define CM_PLLB_HOLDARM BIT(1)
202 # define CM_PLLB_LOADARM BIT(0)
209 # define A2W_PLL_CTRL_PRST_DISABLE BIT(17)
210 # define A2W_PLL_CTRL_PWRDN BIT(16)
212 # define A2W_PLL_CTRL_PDIV_SHIFT 12
239 # define A2W_XOSC_CTRL_PLLB_ENABLE BIT(7)
240 # define A2W_XOSC_CTRL_PLLA_ENABLE BIT(6)
241 # define A2W_XOSC_CTRL_PLLD_ENABLE BIT(5)
242 # define A2W_XOSC_CTRL_DDR_ENABLE BIT(4)
243 # define A2W_XOSC_CTRL_CPR1_ENABLE BIT(3)
244 # define A2W_XOSC_CTRL_USB_ENABLE BIT(2)
245 # define A2W_XOSC_CTRL_HDMI_ENABLE BIT(1)
246 # define A2W_XOSC_CTRL_PLLC_ENABLE BIT(0)
253 # define A2W_PLL_FRAC_MASK ((1 << A2W_PLL_FRAC_BITS) - 1)
256 #define A2W_PLL_CHANNEL_DISABLE BIT(8)
295 #define SOC_BCM2835 BIT(0)
296 #define SOC_BCM2711 BIT(1)
337 writel(CM_PASSWORD | val, cprman->regs + reg);
342 return readl(cprman->regs + reg);
355 spin_lock(&cprman->regs_lock);
372 dev_err(cprman->dev, "timeout waiting for OSCCOUNT\n");
383 dev_err(cprman->dev, "timeout waiting for !BUSY\n");
395 spin_unlock(&cprman->regs_lock);
406 regset = devm_kzalloc(cprman->dev, sizeof(*regset), GFP_KERNEL);
410 regset->regs = regs;
411 regset->nregs = nregs;
412 regset->base = cprman->regs + base;
424 /* Bit in CM_LOCK to indicate when the PLL has locked. */
434 * pre-divide-by-2.
456 .fb_prediv_mask = BIT(14),
466 .fb_prediv_mask = BIT(11),
494 /* Number of integer bits in the divider */
496 /* Number of fractional bits in the divider */
526 struct bcm2835_cprman *cprman = pll->cprman;
527 const struct bcm2835_pll_data *data = pll->data;
529 return cprman_read(cprman, data->a2w_ctrl_reg) &
537 * On BCM2711 there isn't a pre-divisor available in the PLL feedback
538 * loop. Bits 13:14 of ANA1 (PLLA,PLLB,PLLC,PLLD) have been re-purposed
541 if (cprman->soc & SOC_BCM2711)
544 return data->ana->fb_prediv_mask;
557 *fdiv = div & ((1 << A2W_PLL_FRAC_BITS) - 1);
577 const struct bcm2835_pll_data *data = pll->data;
580 req->rate = clamp(req->rate, data->min_rate, data->max_rate);
582 bcm2835_pll_choose_ndiv_and_fdiv(req->rate, req->best_parent_rate,
585 req->rate = bcm2835_pll_rate_from_divisors(req->best_parent_rate,
596 struct bcm2835_cprman *cprman = pll->cprman;
597 const struct bcm2835_pll_data *data = pll->data;
598 u32 a2wctrl = cprman_read(cprman, data->a2w_ctrl_reg);
605 fdiv = cprman_read(cprman, data->frac_reg) & A2W_PLL_FRAC_MASK;
608 using_prediv = cprman_read(cprman, data->ana_reg_base + 4) &
622 struct bcm2835_cprman *cprman = pll->cprman;
623 const struct bcm2835_pll_data *data = pll->data;
625 spin_lock(&cprman->regs_lock);
626 cprman_write(cprman, data->cm_ctrl_reg, CM_PLL_ANARST);
627 cprman_write(cprman, data->a2w_ctrl_reg,
628 cprman_read(cprman, data->a2w_ctrl_reg) |
630 spin_unlock(&cprman->regs_lock);
636 struct bcm2835_cprman *cprman = pll->cprman;
637 const struct bcm2835_pll_data *data = pll->data;
640 cprman_write(cprman, data->a2w_ctrl_reg,
641 cprman_read(cprman, data->a2w_ctrl_reg) &
645 spin_lock(&cprman->regs_lock);
646 cprman_write(cprman, data->cm_ctrl_reg,
647 cprman_read(cprman, data->cm_ctrl_reg) & ~CM_PLL_ANARST);
648 spin_unlock(&cprman->regs_lock);
652 while (!(cprman_read(cprman, CM_LOCK) & data->lock_mask)) {
654 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
656 return -ETIMEDOUT;
662 cprman_write(cprman, data->a2w_ctrl_reg,
663 cprman_read(cprman, data->a2w_ctrl_reg) |
676 * ANA3-ANA0, in that order. This lets us write all 4
679 * 3 individually through their partial-write registers, each
682 for (i = 3; i >= 0; i--)
690 struct bcm2835_cprman *cprman = pll->cprman;
691 const struct bcm2835_pll_data *data = pll->data;
698 if (rate > data->max_fb_rate) {
707 for (i = 3; i >= 0; i--)
708 ana[i] = cprman_read(cprman, data->ana_reg_base + i * 4);
712 ana[0] &= ~data->ana->mask0;
713 ana[0] |= data->ana->set0;
714 ana[1] &= ~data->ana->mask1;
715 ana[1] |= data->ana->set1;
716 ana[3] &= ~data->ana->mask3;
717 ana[3] |= data->ana->set3;
730 spin_lock(&cprman->regs_lock);
733 data->reference_enable_mask);
734 spin_unlock(&cprman->regs_lock);
737 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
740 cprman_write(cprman, data->frac_reg, fdiv);
742 a2w_ctl = cprman_read(cprman, data->a2w_ctrl_reg);
747 cprman_write(cprman, data->a2w_ctrl_reg, a2w_ctl);
750 bcm2835_pll_write_ana(cprman, data->ana_reg_base, ana);
759 struct bcm2835_cprman *cprman = pll->cprman;
760 const struct bcm2835_pll_data *data = pll->data;
763 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
768 regs[0].offset = data->cm_ctrl_reg;
770 regs[1].offset = data->a2w_ctrl_reg;
772 regs[2].offset = data->frac_reg;
774 regs[3].offset = data->ana_reg_base + 0 * 4;
776 regs[4].offset = data->ana_reg_base + 1 * 4;
778 regs[5].offset = data->ana_reg_base + 2 * 4;
780 regs[6].offset = data->ana_reg_base + 3 * 4;
809 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
810 struct bcm2835_cprman *cprman = divider->cprman;
811 const struct bcm2835_pll_divider_data *data = divider->data;
813 return !(cprman_read(cprman, data->a2w_reg) & A2W_PLL_CHANNEL_DISABLE);
830 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
831 struct bcm2835_cprman *cprman = divider->cprman;
832 const struct bcm2835_pll_divider_data *data = divider->data;
834 spin_lock(&cprman->regs_lock);
835 cprman_write(cprman, data->cm_reg,
836 (cprman_read(cprman, data->cm_reg) &
837 ~data->load_mask) | data->hold_mask);
838 cprman_write(cprman, data->a2w_reg,
839 cprman_read(cprman, data->a2w_reg) |
841 spin_unlock(&cprman->regs_lock);
846 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
847 struct bcm2835_cprman *cprman = divider->cprman;
848 const struct bcm2835_pll_divider_data *data = divider->data;
850 spin_lock(&cprman->regs_lock);
851 cprman_write(cprman, data->a2w_reg,
852 cprman_read(cprman, data->a2w_reg) &
855 cprman_write(cprman, data->cm_reg,
856 cprman_read(cprman, data->cm_reg) & ~data->hold_mask);
857 spin_unlock(&cprman->regs_lock);
866 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
867 struct bcm2835_cprman *cprman = divider->cprman;
868 const struct bcm2835_pll_divider_data *data = divider->data;
877 cprman_write(cprman, data->a2w_reg, div);
878 cm = cprman_read(cprman, data->cm_reg);
879 cprman_write(cprman, data->cm_reg, cm | data->load_mask);
880 cprman_write(cprman, data->cm_reg, cm & ~data->load_mask);
888 struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
889 struct bcm2835_cprman *cprman = divider->cprman;
890 const struct bcm2835_pll_divider_data *data = divider->data;
893 regs = devm_kcalloc(cprman->dev, 7, sizeof(*regs), GFP_KERNEL);
898 regs[0].offset = data->cm_reg;
900 regs[1].offset = data->a2w_reg;
916 * The CM dividers do fixed-point division, so we can't use the
917 * generic integer divider code like the PLL dividers do (and we can't
919 * because we'd run out of bits in a 32-bit unsigned long).
935 struct bcm2835_cprman *cprman = clock->cprman;
936 const struct bcm2835_clock_data *data = clock->data;
938 return (cprman_read(cprman, data->ctl_reg) & CM_ENABLE) != 0;
946 const struct bcm2835_clock_data *data = clock->data;
948 GENMASK(CM_DIV_FRAC_BITS - data->frac_bits, 0) >> 1;
957 if (data->is_mash_clock) {
958 /* clamp to min divider of 2 */
960 /* clamp to the highest possible integer divider */
961 maxdiv = (BIT(data->int_bits) - 1) << CM_DIV_FRAC_BITS;
963 /* clamp to min divider of 1 */
965 /* clamp to the highest possible fractional divider */
966 maxdiv = GENMASK(data->int_bits + CM_DIV_FRAC_BITS - 1,
967 CM_DIV_FRAC_BITS - data->frac_bits);
981 const struct bcm2835_clock_data *data = clock->data;
984 if (data->int_bits == 0 && data->frac_bits == 0)
991 div >>= CM_DIV_FRAC_BITS - data->frac_bits;
992 div &= (1 << (data->int_bits + data->frac_bits)) - 1;
997 temp = (u64)parent_rate << data->frac_bits;
1019 if ((rate + scaler - 1) / scaler % 1000 == 0)
1029 struct bcm2835_cprman *cprman = clock->cprman;
1030 const struct bcm2835_clock_data *data = clock->data;
1034 if (data->int_bits == 0 && data->frac_bits == 0)
1037 div = cprman_read(cprman, data->div_reg);
1041 if (data->round_up)
1049 struct bcm2835_cprman *cprman = clock->cprman;
1050 const struct bcm2835_clock_data *data = clock->data;
1053 while (cprman_read(cprman, data->ctl_reg) & CM_BUSY) {
1055 dev_err(cprman->dev, "%s: couldn't lock PLL\n",
1056 clk_hw_get_name(&clock->hw));
1066 struct bcm2835_cprman *cprman = clock->cprman;
1067 const struct bcm2835_clock_data *data = clock->data;
1069 spin_lock(&cprman->regs_lock);
1070 cprman_write(cprman, data->ctl_reg,
1071 cprman_read(cprman, data->ctl_reg) & ~CM_ENABLE);
1072 spin_unlock(&cprman->regs_lock);
1074 /* BUSY will remain high until the divider completes its cycle. */
1081 struct bcm2835_cprman *cprman = clock->cprman;
1082 const struct bcm2835_clock_data *data = clock->data;
1084 spin_lock(&cprman->regs_lock);
1085 cprman_write(cprman, data->ctl_reg,
1086 cprman_read(cprman, data->ctl_reg) |
1089 spin_unlock(&cprman->regs_lock);
1094 if (data->tcnt_mux && false) {
1095 dev_info(cprman->dev,
1096 "clk %s: rate %ld, measure %ld\n",
1097 data->name,
1099 bcm2835_measure_tcnt_mux(cprman, data->tcnt_mux));
1109 struct bcm2835_cprman *cprman = clock->cprman;
1110 const struct bcm2835_clock_data *data = clock->data;
1114 spin_lock(&cprman->regs_lock);
1122 * clk-framework.
1124 ctl = cprman_read(cprman, data->ctl_reg) & ~CM_FRAC;
1126 cprman_write(cprman, data->ctl_reg, ctl);
1128 cprman_write(cprman, data->div_reg, div);
1130 spin_unlock(&cprman->regs_lock);
1152 struct bcm2835_cprman *cprman = clock->cprman;
1153 const struct bcm2835_clock_data *data = clock->data;
1160 if (!(BIT(parent_idx) & data->set_rate_parent)) {
1166 if (data->low_jitter && (*div & CM_DIV_FRAC_MASK)) {
1180 return *avgrate - max(*avgrate - low, high - *avgrate);
1185 if (data->frac_bits)
1186 dev_warn(cprman->dev,
1189 /* clamp to min divider of 2 if we're dealing with a mash clock */
1190 mindiv = data->is_mash_clock ? 2 : 1;
1191 maxdiv = BIT(data->int_bits) - 1;
1236 * Don't choose a PLLC-derived clock as our parent
1239 * over-temp or under-voltage conditions, without
1245 rate = bcm2835_clock_choose_div_and_prate(hw, i, req->rate,
1248 if (abs(req->rate - rate) < abs(req->rate - best_rate)) {
1257 return -EINVAL;
1259 req->best_parent_hw = best_parent;
1260 req->best_parent_rate = best_prate;
1262 req->rate = best_avgrate;
1270 struct bcm2835_cprman *cprman = clock->cprman;
1271 const struct bcm2835_clock_data *data = clock->data;
1274 cprman_write(cprman, data->ctl_reg, src);
1281 struct bcm2835_cprman *cprman = clock->cprman;
1282 const struct bcm2835_clock_data *data = clock->data;
1283 u32 src = cprman_read(cprman, data->ctl_reg);
1303 struct bcm2835_cprman *cprman = clock->cprman;
1304 const struct bcm2835_clock_data *data = clock->data;
1306 bcm2835_debugfs_regset(cprman, data->ctl_reg,
1331 * bit), so it gets its own set of clock ops.
1354 init.parent_names = &cprman->real_parent_names[0];
1356 init.name = pll_data->name;
1358 init.flags = pll_data->flags | CLK_IGNORE_UNUSED;
1364 pll->cprman = cprman;
1365 pll->data = pll_data;
1366 pll->hw.init = &init;
1368 ret = devm_clk_hw_register(cprman->dev, &pll->hw);
1373 return &pll->hw;
1381 struct bcm2835_pll_divider *divider;
1386 if (divider_data->fixed_divider != 1) {
1387 divider_name = devm_kasprintf(cprman->dev, GFP_KERNEL,
1388 "%s_prediv", divider_data->name);
1392 divider_name = divider_data->name;
1397 init.parent_names = ÷r_data->source_pll;
1401 init.flags = divider_data->flags | CLK_IGNORE_UNUSED;
1403 divider = devm_kzalloc(cprman->dev, sizeof(*divider), GFP_KERNEL);
1404 if (!divider)
1407 divider->div.reg = cprman->regs + divider_data->a2w_reg;
1408 divider->div.shift = A2W_PLL_DIV_SHIFT;
1409 divider->div.width = A2W_PLL_DIV_BITS;
1410 divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
1411 divider->div.lock = &cprman->regs_lock;
1412 divider->div.hw.init = &init;
1413 divider->div.table = NULL;
1415 divider->cprman = cprman;
1416 divider->data = divider_data;
1418 ret = devm_clk_hw_register(cprman->dev, ÷r->div.hw);
1426 if (divider_data->fixed_divider != 1) {
1427 return clk_hw_register_fixed_factor(cprman->dev,
1428 divider_data->name,
1432 divider_data->fixed_divider);
1435 return ÷r->div.hw;
1450 * actual clock-output-name of the parent.
1452 for (i = 0; i < clock_data->num_mux_parents; i++) {
1453 parents[i] = clock_data->parents[i];
1459 parents[i] = cprman->real_parent_names[ret];
1464 init.num_parents = clock_data->num_mux_parents;
1465 init.name = clock_data->name;
1466 init.flags = clock_data->flags | CLK_IGNORE_UNUSED;
1472 if (clock_data->set_rate_parent)
1475 if (clock_data->is_vpu_clock) {
1484 if (!(cprman_read(cprman, clock_data->ctl_reg) & CM_ENABLE))
1488 clock = devm_kzalloc(cprman->dev, sizeof(*clock), GFP_KERNEL);
1492 clock->cprman = cprman;
1493 clock->data = clock_data;
1494 clock->hw.init = &init;
1496 ret = devm_clk_hw_register(cprman->dev, &clock->hw);
1499 return &clock->hw;
1507 return clk_hw_register_gate(cprman->dev, gate_data->name,
1508 gate_data->parent,
1510 cprman->regs + gate_data->ctl_reg,
1511 CM_GATE_BIT, 0, &cprman->regs_lock);
1586 "-",
1588 "-",
1589 "-",
1590 "-",
1591 "-",
1593 "-",
1964 .frac_bits = 12),
2003 * Secondary SDRAM clock. Used for low-voltage modes when the PLL
2023 * VPU clock. This doesn't have an enable bit, since it drives
2033 .int_bits = 12,
2106 .int_bits = 12,
2107 .frac_bits = 12,
2115 .int_bits = 12,
2116 .frac_bits = 12,
2125 .int_bits = 12,
2126 .frac_bits = 12,
2143 .int_bits = 12,
2144 .frac_bits = 12,
2153 .int_bits = 12,
2154 .frac_bits = 12,
2162 .int_bits = 12,
2163 .frac_bits = 12,
2180 .frac_bits = 12,
2196 .set_rate_parent = BIT(7),
2223 .tcnt_mux = 12),
2237 * you have the debug bit set in the power manager, which we
2239 * non-stop vpu clock.
2257 static int bcm2835_mark_sdc_parent_critical(struct clk *sdc)
2259 struct clk *parent = clk_get_parent(sdc);
2269 struct device *dev = &pdev->dev;
2278 pdata = of_device_get_match_data(&pdev->dev);
2280 return -ENODEV;
2286 return -ENOMEM;
2288 spin_lock_init(&cprman->regs_lock);
2289 cprman->dev = dev;
2290 cprman->regs = devm_platform_ioremap_resource(pdev, 0);
2291 if (IS_ERR(cprman->regs))
2292 return PTR_ERR(cprman->regs);
2294 memcpy(cprman->real_parent_names, cprman_parent_names,
2296 of_clk_parent_fill(dev->of_node, cprman->real_parent_names,
2306 if (!cprman->real_parent_names[0])
2307 return -ENODEV;
2311 cprman->onecell.num = asize;
2312 cprman->soc = pdata->soc;
2313 hws = cprman->onecell.hws;
2317 if (desc->clk_register && desc->data &&
2318 (desc->supported & pdata->soc)) {
2319 hws[i] = desc->clk_register(cprman, desc->data);
2323 ret = bcm2835_mark_sdc_parent_critical(hws[BCM2835_CLOCK_SDRAM]->clk);
2327 return of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
2328 &cprman->onecell);
2340 { .compatible = "brcm,bcm2835-cprman", .data = &cprman_bcm2835_plat_data },
2341 { .compatible = "brcm,bcm2711-cprman", .data = &cprman_bcm2711_plat_data },
2348 .name = "bcm2835-clk",