57  * Alas we have to mark all PLLs as critical. CPU and DDR PLLs are sources of
59  * shouldn't be ever gated. SATA and PCIe PLLs are the parents of APB-bus and
61  * unusable. Moreover disabling SATA and Ethernet PLLs causes automatic reset
63  * all the devices consuming those PLLs, they will be marked as critical too.
81 	struct ccu_pll *plls[CCU_PLL_NUM];  member
93 			return data->plls[idx];  in ccu_pll_find_desc()
156 		/* Defer non-basic PLLs allocation for the probe stage */  in ccu_pll_clk_register()
158 			if (!data->plls[idx])  in ccu_pll_clk_register()
159 				data->plls[idx] = ERR_PTR(-EPROBE_DEFER);  in ccu_pll_clk_register()
173 		data->plls[idx] = ccu_pll_hw_register(&init);  in ccu_pll_clk_register()
174 		if (IS_ERR(data->plls[idx])) {  in ccu_pll_clk_register()
175 			ret = PTR_ERR(data->plls[idx]);  in ccu_pll_clk_register()
189 		ccu_pll_hw_unregister(data->plls[idx]);  in ccu_pll_clk_register()
204 		ccu_pll_hw_unregister(data->plls[idx]);  in ccu_pll_clk_unregister()