46 static inline bool clk_master_ready(struct clk_master *master)  in clk_master_ready()  argument
48 	unsigned int bit = master->id ? AT91_PMC_MCKXRDY : AT91_PMC_MCKRDY;  in clk_master_ready()
51 	regmap_read(master->regmap, AT91_PMC_SR, &status);  in clk_master_ready()
58 	struct clk_master *master = to_clk_master(hw);  in clk_master_prepare()  local
61 	spin_lock_irqsave(master->lock, flags);  in clk_master_prepare()
63 	while (!clk_master_ready(master))  in clk_master_prepare()
66 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_prepare()
73 	struct clk_master *master = to_clk_master(hw);  in clk_master_is_prepared()  local
77 	spin_lock_irqsave(master->lock, flags);  in clk_master_is_prepared()
78 	status = clk_master_ready(master);  in clk_master_is_prepared()
79 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_is_prepared()
89 	struct clk_master *master = to_clk_master(hw);  in clk_master_div_recalc_rate()  local
90 	const struct clk_master_layout *layout = master->layout;  in clk_master_div_recalc_rate()
92 						master->characteristics;  in clk_master_div_recalc_rate()
95 	spin_lock_irqsave(master->lock, flags);  in clk_master_div_recalc_rate()
96 	regmap_read(master->regmap, master->layout->offset, &mckr);  in clk_master_div_recalc_rate()
97 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_div_recalc_rate()
106 		pr_warn("master clk div is underclocked");  in clk_master_div_recalc_rate()
108 		pr_warn("master clk div is overclocked");  in clk_master_div_recalc_rate()
115 	struct clk_master *master = to_clk_master(hw);  in clk_master_div_save_context()  local
120 	spin_lock_irqsave(master->lock, flags);  in clk_master_div_save_context()
121 	regmap_read(master->regmap, master->layout->offset, &mckr);  in clk_master_div_save_context()
122 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_div_save_context()
124 	mckr &= master->layout->mask;  in clk_master_div_save_context()
126 	div = master->characteristics->divisors[div];  in clk_master_div_save_context()
128 	master->pms.parent_rate = clk_hw_get_rate(parent_hw);  in clk_master_div_save_context()
129 	master->pms.rate = DIV_ROUND_CLOSEST(master->pms.parent_rate, div);  in clk_master_div_save_context()
136 	struct clk_master *master = to_clk_master(hw);  in clk_master_div_restore_context()  local
141 	spin_lock_irqsave(master->lock, flags);  in clk_master_div_restore_context()
142 	regmap_read(master->regmap, master->layout->offset, &mckr);  in clk_master_div_restore_context()
143 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_div_restore_context()
145 	mckr &= master->layout->mask;  in clk_master_div_restore_context()
147 	div = master->characteristics->divisors[div];  in clk_master_div_restore_context()
149 	if (div != DIV_ROUND_CLOSEST(master->pms.parent_rate, master->pms.rate))  in clk_master_div_restore_context()
162 static int clk_master_div_set(struct clk_master *master,  in clk_master_div_set()  argument
166 						master->characteristics;  in clk_master_div_set()
188 	ret = regmap_read(master->regmap, master->layout->offset, &mckr);  in clk_master_div_set()
192 	mckr &= master->layout->mask;  in clk_master_div_set()
199 		pr_warn("master clk div is underclocked");  in clk_master_div_set()
201 		pr_warn("master clk div is overclocked");  in clk_master_div_set()
205 	ret = regmap_write(master->regmap, master->layout->offset, mckr);  in clk_master_div_set()
209 	while (!clk_master_ready(master))  in clk_master_div_set()
212 	master->div = characteristics->divisors[div_index];  in clk_master_div_set()
220 	struct clk_master *master = to_clk_master(hw);  in clk_master_div_recalc_rate_chg()  local
222 	return DIV_ROUND_CLOSEST_ULL(parent_rate, master->div);  in clk_master_div_recalc_rate_chg()
227 	struct clk_master *master = to_clk_master(hw);  in clk_master_div_restore_context_chg()  local
231 	spin_lock_irqsave(master->lock, flags);  in clk_master_div_restore_context_chg()
232 	ret = clk_master_div_set(master, master->pms.parent_rate,  in clk_master_div_restore_context_chg()
233 				 DIV_ROUND_CLOSEST(master->pms.parent_rate,  in clk_master_div_restore_context_chg()
234 						   master->pms.rate));  in clk_master_div_restore_context_chg()
235 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_div_restore_context_chg()
380 	struct clk_master *master = to_clk_master(hw);  in clk_master_pres_recalc_rate()  local
382 						master->characteristics;  in clk_master_pres_recalc_rate()
386 	spin_lock_irqsave(master->lock, flags);  in clk_master_pres_recalc_rate()
387 	regmap_read(master->regmap, master->layout->offset, &val);  in clk_master_pres_recalc_rate()
388 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_pres_recalc_rate()
390 	val &= master->layout->mask;  in clk_master_pres_recalc_rate()
391 	pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;  in clk_master_pres_recalc_rate()
402 	struct clk_master *master = to_clk_master(hw);  in clk_master_pres_get_parent()  local
406 	spin_lock_irqsave(master->lock, flags);  in clk_master_pres_get_parent()
407 	regmap_read(master->regmap, master->layout->offset, &mckr);  in clk_master_pres_get_parent()
408 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_pres_get_parent()
410 	mckr &= master->layout->mask;  in clk_master_pres_get_parent()
417 	struct clk_master *master = to_clk_master(hw);  in clk_master_pres_save_context()  local
422 	spin_lock_irqsave(master->lock, flags);  in clk_master_pres_save_context()
423 	regmap_read(master->regmap, master->layout->offset, &val);  in clk_master_pres_save_context()
424 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_pres_save_context()
426 	val &= master->layout->mask;  in clk_master_pres_save_context()
427 	pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;  in clk_master_pres_save_context()
428 	if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)  in clk_master_pres_save_context()
433 	master->pms.parent = val & AT91_PMC_CSS;  in clk_master_pres_save_context()
434 	master->pms.parent_rate = clk_hw_get_rate(parent_hw);  in clk_master_pres_save_context()
435 	master->pms.rate = DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres);  in clk_master_pres_save_context()
442 	struct clk_master *master = to_clk_master(hw);  in clk_master_pres_restore_context()  local
446 	spin_lock_irqsave(master->lock, flags);  in clk_master_pres_restore_context()
447 	regmap_read(master->regmap, master->layout->offset, &val);  in clk_master_pres_restore_context()
448 	spin_unlock_irqrestore(master->lock, flags);  in clk_master_pres_restore_context()
450 	val &= master->layout->mask;  in clk_master_pres_restore_context()
451 	pres = (val >> master->layout->pres_shift) & MASTER_PRES_MASK;  in clk_master_pres_restore_context()
452 	if (pres == MASTER_PRES_MAX && master->characteristics->have_div3_pres)  in clk_master_pres_restore_context()
457 	if (master->pms.rate !=  in clk_master_pres_restore_context()
458 	    DIV_ROUND_CLOSEST_ULL(master->pms.parent_rate, pres) ||  in clk_master_pres_restore_context()
459 	    (master->pms.parent != (val & AT91_PMC_CSS)))  in clk_master_pres_restore_context()
481 	struct clk_master *master;  in at91_clk_register_master_internal()  local
491 	master = kzalloc(sizeof(*master), GFP_KERNEL);  in at91_clk_register_master_internal()
492 	if (!master)  in at91_clk_register_master_internal()
504 	master->hw.init = &init;  in at91_clk_register_master_internal()
505 	master->layout = layout;  in at91_clk_register_master_internal()
506 	master->characteristics = characteristics;  in at91_clk_register_master_internal()
507 	master->regmap = regmap;  in at91_clk_register_master_internal()
508 	master->lock = lock;  in at91_clk_register_master_internal()
511 		spin_lock_irqsave(master->lock, irqflags);  in at91_clk_register_master_internal()
512 		regmap_read(master->regmap, master->layout->offset, &mckr);  in at91_clk_register_master_internal()
513 		spin_unlock_irqrestore(master->lock, irqflags);  in at91_clk_register_master_internal()
517 		master->div = characteristics->divisors[mckr];  in at91_clk_register_master_internal()
520 	hw = &master->hw;  in at91_clk_register_master_internal()
521 	ret = clk_hw_register(NULL, &master->hw);  in at91_clk_register_master_internal()
523 		kfree(master);  in at91_clk_register_master_internal()
581 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_recalc_rate()  local
583 	return DIV_ROUND_CLOSEST_ULL(parent_rate, (1 << master->div));  in clk_sama7g5_master_recalc_rate()
589 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_determine_rate()  local
618 	if (master->chg_pid < 0)  in clk_sama7g5_master_determine_rate()
621 	parent = clk_hw_get_parent_by_index(hw, master->chg_pid);  in clk_sama7g5_master_determine_rate()
661 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_get_parent()  local
665 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_get_parent()
666 	index = clk_mux_val_to_index(&master->hw, master->mux_table, 0,  in clk_sama7g5_master_get_parent()
667 				     master->parent);  in clk_sama7g5_master_get_parent()
668 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_get_parent()
675 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_set_parent()  local
681 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_set_parent()
682 	master->parent = clk_mux_index_to_val(master->mux_table, 0, index);  in clk_sama7g5_master_set_parent()
683 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_set_parent()
688 static void clk_sama7g5_master_set(struct clk_master *master,  in clk_sama7g5_master_set()  argument
694 	unsigned int parent = master->parent << PMC_MCR_CSS_SHIFT;  in clk_sama7g5_master_set()
695 	unsigned int div = master->div << MASTER_DIV_SHIFT;  in clk_sama7g5_master_set()
697 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_set()
699 	regmap_write(master->regmap, AT91_PMC_MCR_V2,  in clk_sama7g5_master_set()
700 		     AT91_PMC_MCR_V2_ID(master->id));  in clk_sama7g5_master_set()
701 	regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);  in clk_sama7g5_master_set()
702 	regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,  in clk_sama7g5_master_set()
706 			   AT91_PMC_MCR_V2_ID(master->id));  in clk_sama7g5_master_set()
711 	while ((cparent != master->parent) && !clk_master_ready(master))  in clk_sama7g5_master_set()
714 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_set()
719 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_enable()  local
721 	clk_sama7g5_master_set(master, 1);  in clk_sama7g5_master_enable()
728 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_disable()  local
731 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_disable()
733 	regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);  in clk_sama7g5_master_disable()
734 	regmap_update_bits(master->regmap, AT91_PMC_MCR_V2,  in clk_sama7g5_master_disable()
738 			   AT91_PMC_MCR_V2_ID(master->id));  in clk_sama7g5_master_disable()
740 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_disable()
745 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_is_enabled()  local
749 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_is_enabled()
751 	regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);  in clk_sama7g5_master_is_enabled()
752 	regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);  in clk_sama7g5_master_is_enabled()
754 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_is_enabled()
762 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_set_rate()  local
774 	spin_lock_irqsave(master->lock, flags);  in clk_sama7g5_master_set_rate()
775 	master->div = div;  in clk_sama7g5_master_set_rate()
776 	spin_unlock_irqrestore(master->lock, flags);  in clk_sama7g5_master_set_rate()
783 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_save_context()  local
785 	master->pms.status = clk_sama7g5_master_is_enabled(hw);  in clk_sama7g5_master_save_context()
792 	struct clk_master *master = to_clk_master(hw);  in clk_sama7g5_master_restore_context()  local
794 	if (master->pms.status)  in clk_sama7g5_master_restore_context()
795 		clk_sama7g5_master_set(master, master->pms.status);  in clk_sama7g5_master_restore_context()
820 	struct clk_master *master;  in at91_clk_sama7g5_register_master()  local
831 	master = kzalloc(sizeof(*master), GFP_KERNEL);  in at91_clk_sama7g5_register_master()
832 	if (!master)  in at91_clk_sama7g5_register_master()
848 	master->hw.init = &init;  in at91_clk_sama7g5_register_master()
849 	master->regmap = regmap;  in at91_clk_sama7g5_register_master()
850 	master->id = id;  in at91_clk_sama7g5_register_master()
851 	master->chg_pid = chg_pid;  in at91_clk_sama7g5_register_master()
852 	master->lock = lock;  in at91_clk_sama7g5_register_master()
853 	master->mux_table = mux_table;  in at91_clk_sama7g5_register_master()
855 	spin_lock_irqsave(master->lock, flags);  in at91_clk_sama7g5_register_master()
856 	regmap_write(master->regmap, AT91_PMC_MCR_V2, master->id);  in at91_clk_sama7g5_register_master()
857 	regmap_read(master->regmap, AT91_PMC_MCR_V2, &val);  in at91_clk_sama7g5_register_master()
858 	master->parent = (val & AT91_PMC_MCR_V2_CSS) >> PMC_MCR_CSS_SHIFT;  in at91_clk_sama7g5_register_master()
859 	master->div = (val & AT91_PMC_MCR_V2_DIV) >> MASTER_DIV_SHIFT;  in at91_clk_sama7g5_register_master()
860 	spin_unlock_irqrestore(master->lock, flags);  in at91_clk_sama7g5_register_master()
862 	hw = &master->hw;  in at91_clk_sama7g5_register_master()
863 	ret = clk_hw_register(NULL, &master->hw);  in at91_clk_sama7g5_register_master()
865 		kfree(master);  in at91_clk_sama7g5_register_master()