Lines Matching refs:OWL_DIVIDER_HW
249 OWL_DIVIDER_HW(CMU_CSICLK, 0, 4, 0, NULL),
255 OWL_DIVIDER_HW(CMU_CSICLK, 16, 4, 0, NULL),
277 OWL_DIVIDER_HW(CMU_ASSISTPLL, 10, 1, 0, eth_mac_div_table),
307 OWL_DIVIDER_HW(CMU_AUDIOPLL, 24, 4, 0, hdmia_div_table),
337 OWL_DIVIDER_HW(CMU_AUDIOPLL, 20, 4, 0, i2s_div_table),
343 OWL_DIVIDER_HW(CMU_AUDIOPLL, 16, 4, 0, i2s_div_table),
355 OWL_DIVIDER_HW(CMU_LCDCLK, 0, 5, 0, NULL),
361 OWL_DIVIDER_HW(CMU_NANDCCLK, 0, 4, 0, nand_div_table),
367 OWL_DIVIDER_HW(CMU_NANDCCLK, 16, 4, 0, nand_div_table),
372 OWL_DIVIDER_HW(CMU_PWM0CLK, 0, 6, 0, NULL),
377 OWL_DIVIDER_HW(CMU_PWM1CLK, 0, 6, 0, NULL),
388 OWL_DIVIDER_HW(CMU_PWM2CLK, 0, 6, 0, NULL),
393 OWL_DIVIDER_HW(CMU_PWM3CLK, 0, 6, 0, NULL),
398 OWL_DIVIDER_HW(CMU_PWM4CLK, 0, 6, 0, NULL),
403 OWL_DIVIDER_HW(CMU_PWM5CLK, 0, 6, 0, NULL),
433 OWL_DIVIDER_HW(CMU_SENSORCLK, 0, 4, 0, NULL),
439 OWL_DIVIDER_HW(CMU_TLSCLK, 0, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
445 OWL_DIVIDER_HW(CMU_TLSCLK, 8, 4, CLK_DIVIDER_POWER_OF_TWO, NULL),
451 OWL_DIVIDER_HW(CMU_UART0CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
457 OWL_DIVIDER_HW(CMU_UART1CLK, 1, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
463 OWL_DIVIDER_HW(CMU_UART2CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
469 OWL_DIVIDER_HW(CMU_UART3CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
475 OWL_DIVIDER_HW(CMU_UART4CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
481 OWL_DIVIDER_HW(CMU_UART5CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),
487 OWL_DIVIDER_HW(CMU_UART6CLK, 0, 8, CLK_DIVIDER_ROUND_CLOSEST, NULL),