1 // SPDX-License-Identifier: GPL-2.0-or-later
3  * APM X-Gene SoC RNG Driver
94 	disable_irq(ctx->irq);  in xgene_rng_expired_timer()
95 	ctx->failure_cnt = 0;  in xgene_rng_expired_timer()
96 	timer_delete(&ctx->failure_timer);  in xgene_rng_expired_timer()
97 	enable_irq(ctx->irq);  in xgene_rng_expired_timer()
102 	ctx->failure_timer.expires = jiffies + 120 * HZ;  in xgene_rng_start_timer()
103 	add_timer(&ctx->failure_timer);  in xgene_rng_start_timer()
111 	writel(fro_val, ctx->csr_base + RNG_FRODETUNE);  in xgene_rng_init_fro()
112 	writel(0x00000000, ctx->csr_base + RNG_ALARMMASK);  in xgene_rng_init_fro()
113 	writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP);  in xgene_rng_init_fro()
114 	writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE);  in xgene_rng_init_fro()
121 	val = readl(ctx->csr_base + RNG_INTR_STS_ACK);  in xgene_rng_chk_overflow()
124 		 * LFSR detected an out-of-bounds number of 1s after  in xgene_rng_chk_overflow()
126 		 * AIS-31 standard)  in xgene_rng_chk_overflow()
128 		dev_err(ctx->dev, "test monobit failure error 0x%08X\n", val);  in xgene_rng_chk_overflow()
131 		 * LFSR detected an out-of-bounds value in at least one  in xgene_rng_chk_overflow()
134 		 * specified in the AIS-31 standard)  in xgene_rng_chk_overflow()
136 		dev_err(ctx->dev, "test poker failure error 0x%08X\n", val);  in xgene_rng_chk_overflow()
140 		 * (test T4 as specified in the AIS-31 standard)  in xgene_rng_chk_overflow()
142 		dev_err(ctx->dev, "test long run failure error 0x%08X\n", val);  in xgene_rng_chk_overflow()
145 		 * LFSR detected an outof-bounds value for at least one  in xgene_rng_chk_overflow()
147 		 * (test T3 as specified in the AIS-31 standard)  in xgene_rng_chk_overflow()
149 		dev_err(ctx->dev, "test run failure error 0x%08X\n", val);  in xgene_rng_chk_overflow()
152 		dev_err(ctx->dev, "noise failure error 0x%08X\n", val);  in xgene_rng_chk_overflow()
158 		dev_err(ctx->dev, "stuck out failure error 0x%08X\n", val);  in xgene_rng_chk_overflow()
164 		if (++ctx->failure_cnt == 1) {  in xgene_rng_chk_overflow()
166 			ctx->failure_ts = jiffies;  in xgene_rng_chk_overflow()
167 			frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);  in xgene_rng_chk_overflow()
177 			if (time_after(ctx->failure_ts + 60 * HZ, jiffies)) {  in xgene_rng_chk_overflow()
178 				dev_err(ctx->dev,  in xgene_rng_chk_overflow()
179 					"FRO shutdown failure error 0x%08X\n",  in xgene_rng_chk_overflow()
183 				ctx->failure_ts = jiffies;  in xgene_rng_chk_overflow()
184 				ctx->failure_cnt = 1;  in xgene_rng_chk_overflow()
192 			frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);  in xgene_rng_chk_overflow()
197 	writel(val, ctx->csr_base + RNG_INTR_STS_ACK);  in xgene_rng_chk_overflow()
212 	struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;  in xgene_rng_data_present()
216 		val = readl(ctx->csr_base + RNG_INTR_STS_ACK);  in xgene_rng_data_present()
227 	struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;  in xgene_rng_data_read()
230 	for (i = 0; i < ctx->datum_size; i++)  in xgene_rng_data_read()
231 		data[i] = readl(ctx->csr_base + RNG_INOUT_0 + i * 4);  in xgene_rng_data_read()
234 	writel(READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);  in xgene_rng_data_read()
236 	return ctx->datum_size << 2;  in xgene_rng_data_read()
243 	writel(0x00000000, ctx->csr_base + RNG_CONTROL);  in xgene_rng_init_internal()
247 	writel(val, ctx->csr_base + RNG_CONFIG);  in xgene_rng_init_internal()
250 	writel(val, ctx->csr_base + RNG_ALARMCNT);  in xgene_rng_init_internal()
261 		READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);  in xgene_rng_init_internal()
271 	writel(val, ctx->csr_base + RNG_CONTROL);  in xgene_rng_init_internal()
276 	struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;  in xgene_rng_init()
278 	ctx->failure_cnt = 0;  in xgene_rng_init()
279 	timer_setup(&ctx->failure_timer, xgene_rng_expired_timer, 0);  in xgene_rng_init()
281 	ctx->revision = readl(ctx->csr_base + RNG_EIP_REV);  in xgene_rng_init()
283 	dev_dbg(ctx->dev, "Rev %d.%d.%d\n",  in xgene_rng_init()
284 		MAJOR_HW_REV_RD(ctx->revision),  in xgene_rng_init()
285 		MINOR_HW_REV_RD(ctx->revision),  in xgene_rng_init()
286 		HW_PATCH_LEVEL_RD(ctx->revision));  in xgene_rng_init()
288 	dev_dbg(ctx->dev, "Options 0x%08X",  in xgene_rng_init()
289 		readl(ctx->csr_base + RNG_OPTIONS));  in xgene_rng_init()
293 	ctx->datum_size = RNG_MAX_DATUM;  in xgene_rng_init()
307 	.name		= "xgene-rng",
319 	ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);  in xgene_rng_probe()
321 		return -ENOMEM;  in xgene_rng_probe()
323 	ctx->dev = &pdev->dev;  in xgene_rng_probe()
325 	ctx->csr_base = devm_platform_ioremap_resource(pdev, 0);  in xgene_rng_probe()
326 	if (IS_ERR(ctx->csr_base))  in xgene_rng_probe()
327 		return PTR_ERR(ctx->csr_base);  in xgene_rng_probe()
332 	ctx->irq = rc;  in xgene_rng_probe()
334 	dev_dbg(&pdev->dev, "APM X-Gene RNG BASE %p ALARM IRQ %d",  in xgene_rng_probe()
335 		ctx->csr_base, ctx->irq);  in xgene_rng_probe()
337 	rc = devm_request_irq(&pdev->dev, ctx->irq, xgene_rng_irq_handler, 0,  in xgene_rng_probe()
338 				dev_name(&pdev->dev), ctx);  in xgene_rng_probe()
340 		return dev_err_probe(&pdev->dev, rc, "Could not request RNG alarm IRQ\n");  in xgene_rng_probe()
343 	clk = devm_clk_get_optional_enabled(&pdev->dev, NULL);  in xgene_rng_probe()
345 		return dev_err_probe(&pdev->dev, PTR_ERR(clk), "Couldn't get the clock for RNG\n");  in xgene_rng_probe()
349 	rc = devm_hwrng_register(&pdev->dev, &xgene_rng_func);  in xgene_rng_probe()
351 		return dev_err_probe(&pdev->dev, rc, "RNG registering failed\n");  in xgene_rng_probe()
353 	rc = device_init_wakeup(&pdev->dev, 1);  in xgene_rng_probe()
355 		return dev_err_probe(&pdev->dev, rc, "RNG device_init_wakeup failed\n");  in xgene_rng_probe()
364 	rc = device_init_wakeup(&pdev->dev, 0);  in xgene_rng_remove()
366 		dev_err(&pdev->dev, "RNG init wakeup failed error %d\n", rc);  in xgene_rng_remove()
370 	{ .compatible = "apm,xgene-rng" },
380 		.name		= "xgene-rng",
387 MODULE_DESCRIPTION("APM X-Gene RNG driver");