Lines Matching +full:0 +full:x133

11 #define RNG_v1_CTL_WAIT       0x0000000001fffe00ULL /* Minimum wait time    */
13 #define RNG_v1_CTL_BYPASS     0x0000000000000100ULL /* VCO voltage source   */
14 #define RNG_v1_CTL_VCO        0x00000000000000c0ULL /* VCO rate control     */
16 #define RNG_v1_CTL_ASEL       0x0000000000000030ULL /* Analog MUX select    */
21 #define RNG_CTL_LFSR       0x0000000000000008ULL /* Use LFSR or plain shift */
22 #define RNG_CTL_ES3        0x0000000000000004ULL /* Enable entropy source 3 */
23 #define RNG_CTL_ES2        0x0000000000000002ULL /* Enable entropy source 2 */
24 #define RNG_CTL_ES1        0x0000000000000001ULL /* Enable entropy source 1 */
27 #define RNG_v2_CTL_WAIT       0x0000000007fff800ULL /* Minimum wait time    */
29 #define RNG_v2_CTL_BYPASS     0x0000000000000400ULL /* VCO voltage source   */
30 #define RNG_v2_CTL_VCO        0x0000000000000300ULL /* VCO rate control     */
32 #define RNG_v2_CTL_PERF       0x0000000000000180ULL /* Perf */
33 #define RNG_v2_CTL_ASEL       0x0000000000000070ULL /* Analog MUX select    */
38 #define HV_FAST_RNG_GET_DIAG_CTL	0x130
39 #define HV_FAST_RNG_CTL_READ		0x131
40 #define HV_FAST_RNG_CTL_WRITE		0x132
41 #define HV_FAST_RNG_DATA_READ_DIAG	0x133
42 #define HV_FAST_RNG_DATA_READ		0x134
44 #define HV_RNG_STATE_UNCONFIGURED	0
102 #define N2RNG_FLAG_MULTI	0x00000001 /* Multi-unit capable RNG */
103 #define N2RNG_FLAG_CONTROL	0x00000002 /* Operating in control domain */
104 #define N2RNG_FLAG_READY	0x00000008 /* Ready for hw-rng layer      */
105 #define N2RNG_FLAG_SHUTDOWN	0x00000010 /* Driver unregistering        */
106 #define N2RNG_FLAG_BUFFER_VALID	0x00000020 /* u32 buffer holds valid data */
126 #define N2RNG_HEALTH_CHECK_SEC_DEFAULT	0
128 #define N2RNG_WD_TIMEO_DEFAULT		0
133 #define RNG_v1_SELFTEST_VAL	((u64)0xB8820C7BD387E32C)
135 #define RNG_v2_SELFTEST_VAL	((u64)0xffffffffffffffff)
136 #define SELFTEST_POLY		((u64)0x231DCEE91262B8A3)