Lines Matching +full:stm32 +full:- +full:rng
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2023, STMicroelectronics - All Rights Reserved
359 "RNG",
450 const struct stm32_rifsc_resources_names *dbg_names = rifsc->res_names; in stm32_rifsc_fill_rimu_dbg_entry()
451 u32 rimc_attr = readl_relaxed(rifsc->mmio + RIFSC_RIMC_ATTR0 + 0x4 * i); in stm32_rifsc_fill_rimu_dbg_entry()
453 snprintf(dbg_entry->m_name, sizeof(dbg_entry->m_name), "%s", dbg_names->initiator_names[i]); in stm32_rifsc_fill_rimu_dbg_entry()
454 dbg_entry->m_cid = FIELD_GET(RIFSC_RIMC_MCID_MASK, rimc_attr); in stm32_rifsc_fill_rimu_dbg_entry()
455 dbg_entry->cidsel = rimc_attr & RIFSC_RIMC_CIDSEL; in stm32_rifsc_fill_rimu_dbg_entry()
456 dbg_entry->m_sec = rimc_attr & RIFSC_RIMC_MSEC; in stm32_rifsc_fill_rimu_dbg_entry()
457 dbg_entry->m_priv = rimc_attr & RIFSC_RIMC_MPRIV; in stm32_rifsc_fill_rimu_dbg_entry()
463 const struct stm32_rifsc_resources_names *dbg_names = rifsc->res_names; in stm32_rifsc_fill_dev_dbg_entry()
468 cid_cfgr = readl_relaxed(rifsc->mmio + RIFSC_RISC_PER0_CIDCFGR + 0x8 * i); in stm32_rifsc_fill_dev_dbg_entry()
469 sec_cfgr = readl_relaxed(rifsc->mmio + RIFSC_RISC_SECCFGR0 + 0x4 * reg_id); in stm32_rifsc_fill_dev_dbg_entry()
470 priv_cfgr = readl_relaxed(rifsc->mmio + RIFSC_RISC_PRIVCFGR0 + 0x4 * reg_id); in stm32_rifsc_fill_dev_dbg_entry()
472 snprintf(dbg_entry->dev_name, sizeof(dbg_entry->dev_name), "%s", in stm32_rifsc_fill_dev_dbg_entry()
473 dbg_names->device_names[i]); in stm32_rifsc_fill_dev_dbg_entry()
474 dbg_entry->dev_id = i; in stm32_rifsc_fill_dev_dbg_entry()
475 dbg_entry->dev_cid_filt_en = cid_cfgr & CIDCFGR_CFEN; in stm32_rifsc_fill_dev_dbg_entry()
476 dbg_entry->dev_sem_en = cid_cfgr & CIDCFGR_SEMEN; in stm32_rifsc_fill_dev_dbg_entry()
477 dbg_entry->dev_cid = FIELD_GET(RIFSC_RISC_SCID_MASK, cid_cfgr); in stm32_rifsc_fill_dev_dbg_entry()
478 dbg_entry->dev_sem_cids = FIELD_GET(RIFSC_RISC_SEMWL_MASK, cid_cfgr); in stm32_rifsc_fill_dev_dbg_entry()
479 dbg_entry->dev_sec = sec_cfgr & BIT(reg_offset) ? true : false; in stm32_rifsc_fill_dev_dbg_entry()
480 dbg_entry->dev_priv = priv_cfgr & BIT(reg_offset) ? true : false; in stm32_rifsc_fill_dev_dbg_entry()
488 u32 risc_xcfgr = readl_relaxed(rifsc->mmio + RIFSC_RISC_REG0_ACFGR + 0x10 * i + 0x8 * j); in stm32_rifsc_fill_subreg_dbg_entry()
491 dbg_entry->sr_sec = risc_xcfgr & RIFSC_RISC_SRSEC; in stm32_rifsc_fill_subreg_dbg_entry()
492 dbg_entry->sr_priv = risc_xcfgr & RIFSC_RISC_SRPRIV; in stm32_rifsc_fill_subreg_dbg_entry()
493 dbg_entry->sr_cid = FIELD_GET(RIFSC_RISC_SRCID_MASK, risc_xcfgr); in stm32_rifsc_fill_subreg_dbg_entry()
494 dbg_entry->sr_rlock = risc_xcfgr & RIFSC_RISC_SRRLOCK; in stm32_rifsc_fill_subreg_dbg_entry()
495 dbg_entry->sr_enable = risc_xcfgr & RIFSC_RISC_SREN; in stm32_rifsc_fill_subreg_dbg_entry()
497 risc_xaddr = readl_relaxed(rifsc->mmio + RIFSC_RISC_REG3_AADDR + 0x8 * j); in stm32_rifsc_fill_subreg_dbg_entry()
498 dbg_entry->sr_length = FIELD_GET(RIFSC_RISC_SRLENGTH_MASK, risc_xaddr); in stm32_rifsc_fill_subreg_dbg_entry()
499 dbg_entry->sr_start = FIELD_GET(RIFSC_RISC_SRSTART_MASK, risc_xaddr); in stm32_rifsc_fill_subreg_dbg_entry()
501 dbg_entry->sr_start = 0; in stm32_rifsc_fill_subreg_dbg_entry()
502 dbg_entry->sr_length = U16_MAX; in stm32_rifsc_fill_subreg_dbg_entry()
508 struct rifsc_dbg_private *rifsc = (struct rifsc_dbg_private *)s->private; in stm32_rifsc_conf_dump_show()
519 seq_printf(s, "\n| %-15s |", "Peripheral name"); in stm32_rifsc_conf_dump_show()
528 for (i = 0; i < RIFSC_RISUP_ENTRIES && i < rifsc->nb_risup; i++) { in stm32_rifsc_conf_dump_show()
533 seq_printf(s, "| %-15s |", d_dbg_entry.dev_name); in stm32_rifsc_conf_dump_show()
534 seq_printf(s, "| %-11d |", d_dbg_entry.dev_id); in stm32_rifsc_conf_dump_show()
535 seq_printf(s, "| %-8s |", d_dbg_entry.dev_sec ? "SEC" : "NSEC"); in stm32_rifsc_conf_dump_show()
536 seq_printf(s, "| %-12s |", d_dbg_entry.dev_priv ? "PRIV" : "NPRIV"); in stm32_rifsc_conf_dump_show()
537 seq_printf(s, "| %-13s |", str_enabled_disabled(d_dbg_entry.dev_cid_filt_en)); in stm32_rifsc_conf_dump_show()
538 seq_printf(s, "| %-14s |", str_enabled_disabled(d_dbg_entry.dev_sem_en)); in stm32_rifsc_conf_dump_show()
539 seq_printf(s, "| %-4d |", d_dbg_entry.dev_cid); in stm32_rifsc_conf_dump_show()
540 seq_printf(s, "| %#-7x |\n", d_dbg_entry.dev_sem_cids); in stm32_rifsc_conf_dump_show()
553 for (i = 0; i < RIFSC_RIMU_ENTRIES && rifsc->nb_rimu; i++) { in stm32_rifsc_conf_dump_show()
558 seq_printf(s, "| %-11s |", m_dbg_entry.m_name); in stm32_rifsc_conf_dump_show()
559 seq_printf(s, "| %-6s |", m_dbg_entry.cidsel ? "CIDSEL" : ""); in stm32_rifsc_conf_dump_show()
560 seq_printf(s, "| %-4d |", m_dbg_entry.m_cid); in stm32_rifsc_conf_dump_show()
561 seq_printf(s, "| %-8s |", m_dbg_entry.m_sec ? "SEC" : "NSEC"); in stm32_rifsc_conf_dump_show()
562 seq_printf(s, "| %-12s |\n", m_dbg_entry.m_priv ? "PRIV" : "NPRIV"); in stm32_rifsc_conf_dump_show()
565 if (rifsc->nb_risal > 0) { in stm32_rifsc_conf_dump_show()
580 for (i = 0; i < rifsc->nb_risal; i++) { in stm32_rifsc_conf_dump_show()
588 seq_printf(s, "| %-8s |", sr_dbg_entry.sr_sec ? "SEC" : "NSEC"); in stm32_rifsc_conf_dump_show()
589 seq_printf(s, "| %-12s |", sr_dbg_entry.sr_priv ? "PRIV" : "NPRIV"); in stm32_rifsc_conf_dump_show()
590 seq_printf(s, "| 0x%-9x |", sr_dbg_entry.sr_cid); in stm32_rifsc_conf_dump_show()
591 seq_printf(s, "| %-13s |", in stm32_rifsc_conf_dump_show()
593 seq_printf(s, "| %-14s |", in stm32_rifsc_conf_dump_show()
595 seq_printf(s, "| 0x%-11x |", sr_dbg_entry.sr_start); in stm32_rifsc_conf_dump_show()
596 seq_printf(s, "| 0x%-11x |\n", sr_dbg_entry.sr_start + in stm32_rifsc_conf_dump_show()
597 sr_dbg_entry.sr_length - 1); in stm32_rifsc_conf_dump_show()
612 rifsc_priv = devm_kzalloc(rifsc_controller->dev, sizeof(*rifsc_priv), GFP_KERNEL); in stm32_rifsc_register_debugfs()
614 return -ENOMEM; in stm32_rifsc_register_debugfs()
616 rifsc_priv->mmio = rifsc_controller->mmio; in stm32_rifsc_register_debugfs()
617 rifsc_priv->nb_risup = nb_risup; in stm32_rifsc_register_debugfs()
618 rifsc_priv->nb_rimu = nb_rimu; in stm32_rifsc_register_debugfs()
619 rifsc_priv->nb_risal = nb_risal; in stm32_rifsc_register_debugfs()
620 rifsc_priv->res_names = of_device_get_match_data(rifsc_controller->dev); in stm32_rifsc_register_debugfs()
643 void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id; in stm32_rif_acquire_semaphore()
650 return -EACCES; in stm32_rif_acquire_semaphore()
658 void __iomem *addr = stm32_firewall_controller->mmio + RIFSC_RISC_PER0_SEMCR + 0x8 * id; in stm32_rif_release_semaphore()
676 if (firewall_id >= rifsc_controller->max_entries) { in stm32_rifsc_grant_access()
677 dev_err(rifsc_controller->dev, "Invalid sys bus ID %u", firewall_id); in stm32_rifsc_grant_access()
678 return -EINVAL; in stm32_rifsc_grant_access()
688 sec_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_SECCFGR0 + 0x4 * reg_id); in stm32_rifsc_grant_access()
689 cid_reg_value = readl(rifsc_controller->mmio + RIFSC_RISC_PER0_CIDCFGR + 0x8 * firewall_id); in stm32_rifsc_grant_access()
697 dev_dbg(rifsc_controller->dev, in stm32_rifsc_grant_access()
699 return -EACCES; in stm32_rifsc_grant_access()
713 dev_dbg(rifsc_controller->dev, "Invalid CID configuration for peripheral: %d\n", in stm32_rifsc_grant_access()
715 return -EACCES; in stm32_rifsc_grant_access()
721 dev_dbg(rifsc_controller->dev, in stm32_rifsc_grant_access()
723 return -EACCES; in stm32_rifsc_grant_access()
733 dev_err(rifsc_controller->dev, in stm32_rifsc_grant_access()
750 struct device_node *np = pdev->dev.of_node; in stm32_rifsc_probe()
756 rifsc_controller = devm_kzalloc(&pdev->dev, sizeof(*rifsc_controller), GFP_KERNEL); in stm32_rifsc_probe()
758 return -ENOMEM; in stm32_rifsc_probe()
764 rifsc_controller->dev = &pdev->dev; in stm32_rifsc_probe()
765 rifsc_controller->mmio = mmio; in stm32_rifsc_probe()
766 rifsc_controller->name = dev_driver_string(rifsc_controller->dev); in stm32_rifsc_probe()
767 rifsc_controller->type = STM32_PERIPHERAL_FIREWALL | STM32_MEMORY_FIREWALL; in stm32_rifsc_probe()
768 rifsc_controller->grant_access = stm32_rifsc_grant_access; in stm32_rifsc_probe()
769 rifsc_controller->release_access = stm32_rifsc_release_access; in stm32_rifsc_probe()
773 readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2)); in stm32_rifsc_probe()
775 readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2)); in stm32_rifsc_probe()
777 readl(rifsc_controller->mmio + RIFSC_RISC_HWCFGR2)); in stm32_rifsc_probe()
780 * instead of 0). A software workaround is implemented using the st,mem-map property in the in stm32_rifsc_probe()
783 if (of_device_is_compatible(np, "st,stm32mp21-rifsc")) in stm32_rifsc_probe()
785 rifsc_controller->max_entries = nb_risup + nb_rimu + nb_risal; in stm32_rifsc_probe()
791 dev_err(rifsc_controller->dev, "Couldn't register as a firewall controller: %d", in stm32_rifsc_probe()
798 dev_err(rifsc_controller->dev, "Couldn't populate RIFSC bus: %d", in stm32_rifsc_probe()
806 return dev_err_probe(rifsc_controller->dev, rc, "Failed creating debugfs entry\n"); in stm32_rifsc_probe()
810 return of_platform_populate(np, NULL, NULL, &pdev->dev); in stm32_rifsc_probe()
815 .compatible = "st,stm32mp25-rifsc",
821 .compatible = "st,stm32mp21-rifsc",
833 .name = "stm32-rifsc",