1 // SPDX-License-Identifier: GPL-2.0-only
11  * - One to configure the access of the CPU to the devices. Depending
17  * - One to configure the access to the CPU to the SDRAM. There are
23  * - Reads out the SDRAM address decoding windows at initialization
25  *   information. The exported function mv_mbus_dram_info() allow
30  *   devices have to configure those device -> SDRAM windows to ensure
33  * - Provides an API for platform code or device drivers to
34  *   dynamically add or remove address decoding windows for the CPU ->
39  * - Provides a debugfs interface in /sys/kernel/debug/mvebu-mbus/ to
40  *   see the list of CPU -> SDRAM windows and their configuration
41  *   (file 'sdram') and the list of CPU -> devices windows and their
156  * - The normal one, where the described DRAM ranges may overlap with
162  * - The 'nooverlap' one, where the described DRAM ranges are
167  *   the crypto SRAM (which is mapped through an I/O window) and a
190 	return mbus->soc->win_remap_offset(win) != MVEBU_MBUS_NO_REMAP;  in mvebu_mbus_window_is_remappable()
202 	void __iomem *addr = mbus->mbuswins_base +  in mvebu_mbus_read_window()
203 		mbus->soc->win_cfg_offset(win);  in mvebu_mbus_read_window()
226 			void __iomem *addr_rmp = mbus->mbuswins_base +  in mvebu_mbus_read_window()
227 				mbus->soc->win_remap_offset(win);  in mvebu_mbus_read_window()
241 	addr = mbus->mbuswins_base + mbus->soc->win_cfg_offset(win);  in mvebu_mbus_disable_window()
246 		addr = mbus->mbuswins_base + mbus->soc->win_remap_offset(win);  in mvebu_mbus_disable_window()
257 	void __iomem *addr = mbus->mbuswins_base +  in mvebu_mbus_window_is_free()
258 		mbus->soc->win_cfg_offset(win);  in mvebu_mbus_window_is_free()
275 	for (win = 0; win < mbus->soc->num_wins; win++) {  in mvebu_mbus_window_conflicts()
306 	for (win = 0; win < mbus->soc->num_wins; win++) {  in mvebu_mbus_find_window()
322 	return -ENODEV;  in mvebu_mbus_find_window()
330 	void __iomem *addr = mbus->mbuswins_base +  in mvebu_mbus_setup_window()
331 		mbus->soc->win_cfg_offset(win);  in mvebu_mbus_setup_window()
336 		return -EINVAL;  in mvebu_mbus_setup_window()
339 	if ((base & (phys_addr_t)(size - 1)) != 0) {  in mvebu_mbus_setup_window()
342 		return -EINVAL;  in mvebu_mbus_setup_window()
345 	ctrl = ((size - 1) & WIN_CTRL_SIZE_MASK) |  in mvebu_mbus_setup_window()
349 	if (mbus->hw_io_coherency)  in mvebu_mbus_setup_window()
356 		void __iomem *addr_rmp = mbus->mbuswins_base +  in mvebu_mbus_setup_window()
357 			mbus->soc->win_remap_offset(win);  in mvebu_mbus_setup_window()
378 		for (win = 0; win < mbus->soc->num_wins; win++) {  in mvebu_mbus_alloc_window()
389 	for (win = 0; win < mbus->soc->num_wins; win++) {  in mvebu_mbus_alloc_window()
400 	return -ENOMEM;  in mvebu_mbus_alloc_window()
414 		u32 basereg = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));  in mvebu_sdram_debug_show_orion()
415 		u32 sizereg = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));  in mvebu_sdram_debug_show_orion()
428 		seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",  in mvebu_sdram_debug_show_orion()
444 		u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));  in mvebu_sdram_debug_show_dove()
454 		size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);  in mvebu_sdram_debug_show_dove()
456 		seq_printf(seq, "[%d] %016llx - %016llx : cs%d\n",  in mvebu_sdram_debug_show_dove()
467 	return mbus->soc->show_cpu_target(mbus, seq, v);  in mvebu_sdram_debug_show()
476 	for (win = 0; win < mbus->soc->num_wins; win++) {  in mvebu_devs_debug_show()
491 		seq_printf(seq, "[%02d] %016llx - %016llx : %04x:%04x",  in mvebu_devs_debug_show()
496 		    ((wbase & (u64)(wsize - 1)) != 0))  in mvebu_devs_debug_show()
511  * SoC-specific functions and definitions
523 	 * - At offset 0x0, there are the registers for the first 8  in armada_370_xp_mbus_win_cfg_offset()
526 	 * - Then at offset 0x80, there is a hole of 0x10 bytes for  in armada_370_xp_mbus_win_cfg_offset()
529 	 * - Then at offset 0x90, there the registers for 12  in armada_370_xp_mbus_win_cfg_offset()
536 		return 0x90 + ((win - 8) << 3);  in armada_370_xp_mbus_win_cfg_offset()
544 		return 0x900 + ((win - 8) << 4);  in mv78xx0_mbus_win_cfg_offset()
576 		return 0xF0 - WIN_REMAP_LO_OFF;  in armada_xp_mbus_win_remap_offset()
630 		base = w->base;  in mvebu_mbus_setup_cpu_target_nooverlap()
631 		size = w->size;  in mvebu_mbus_setup_cpu_target_nooverlap()
646 			size -= mbus_bridge_end - base;  in mvebu_mbus_setup_cpu_target_nooverlap()
655 			size -= end - mbus_bridge_base;  in mvebu_mbus_setup_cpu_target_nooverlap()
658 		w->cs_index = i;  in mvebu_mbus_setup_cpu_target_nooverlap()
659 		w->mbus_attr = 0xf & ~(1 << i);  in mvebu_mbus_setup_cpu_target_nooverlap()
660 		if (mbus->hw_io_coherency)  in mvebu_mbus_setup_cpu_target_nooverlap()
661 			w->mbus_attr |= ATTR_HW_COHERENCY;  in mvebu_mbus_setup_cpu_target_nooverlap()
662 		w->base = base;  in mvebu_mbus_setup_cpu_target_nooverlap()
663 		w->size = size;  in mvebu_mbus_setup_cpu_target_nooverlap()
679 		u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));  in mvebu_mbus_default_setup_cpu_target()
680 		u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));  in mvebu_mbus_default_setup_cpu_target()
693 			w->cs_index = i;  in mvebu_mbus_default_setup_cpu_target()
694 			w->mbus_attr = 0xf & ~(1 << i);  in mvebu_mbus_default_setup_cpu_target()
695 			if (mbus->hw_io_coherency)  in mvebu_mbus_default_setup_cpu_target()
696 				w->mbus_attr |= ATTR_HW_COHERENCY;  in mvebu_mbus_default_setup_cpu_target()
697 			w->base = base & DDR_BASE_CS_LOW_MASK;  in mvebu_mbus_default_setup_cpu_target()
698 			w->size = (u64)(size | ~DDR_SIZE_MASK) + 1;  in mvebu_mbus_default_setup_cpu_target()
711 		u32 base = readl(mbus->sdramwins_base + DDR_BASE_CS_OFF(i));  in mvebu_mbus_default_save_cpu_target()
712 		u32 size = readl(mbus->sdramwins_base + DDR_SIZE_CS_OFF(i));  in mvebu_mbus_default_save_cpu_target()
714 		writel(mbus->sdramwins_phys_base + DDR_BASE_CS_OFF(i),  in mvebu_mbus_default_save_cpu_target()
717 		writel(mbus->sdramwins_phys_base + DDR_SIZE_CS_OFF(i),  in mvebu_mbus_default_save_cpu_target()
735 		u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));  in mvebu_mbus_dove_setup_cpu_target()
744 			w->cs_index = i;  in mvebu_mbus_dove_setup_cpu_target()
745 			w->mbus_attr = 0; /* CS address decoding done inside */  in mvebu_mbus_dove_setup_cpu_target()
748 			w->base = map & 0xff800000;  in mvebu_mbus_dove_setup_cpu_target()
749 			w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4);  in mvebu_mbus_dove_setup_cpu_target()
763 		u32 map = readl(mbus->sdramwins_base + DOVE_DDR_BASE_CS_OFF(i));  in mvebu_mbus_dove_save_cpu_target()
765 		writel(mbus->sdramwins_phys_base + DOVE_DDR_BASE_CS_OFF(i),  in mvebu_mbus_dove_save_cpu_target()
776 	return mbus_state.soc->save_cpu_target(&mbus_state, store_addr);  in mvebu_mbus_save_cpu_target()
849 	{ .compatible = "marvell,armada370-mbus",
851 	{ .compatible = "marvell,armada375-mbus",
853 	{ .compatible = "marvell,armada380-mbus",
855 	{ .compatible = "marvell,armadaxp-mbus",
857 	{ .compatible = "marvell,kirkwood-mbus",
859 	{ .compatible = "marvell,dove-mbus",
861 	{ .compatible = "marvell,orion5x-88f5281-mbus",
863 	{ .compatible = "marvell,orion5x-88f5182-mbus",
865 	{ .compatible = "marvell,orion5x-88f5181-mbus",
867 	{ .compatible = "marvell,orion5x-88f6183-mbus",
869 	{ .compatible = "marvell,mv78xx0-mbus",
887 		return -EINVAL;  in mvebu_mbus_add_window_remap_by_id()
940 		return -ENODEV;  in mvebu_mbus_get_dram_win_info()
944 	for (i = 0; i < dram->num_cs; i++) {  in mvebu_mbus_get_dram_win_info()
945 		const struct mbus_dram_window *cs = dram->cs + i;  in mvebu_mbus_get_dram_win_info()
947 		if (cs->base <= phyaddr &&  in mvebu_mbus_get_dram_win_info()
948 			phyaddr <= (cs->base + cs->size - 1)) {  in mvebu_mbus_get_dram_win_info()
949 			*target = dram->mbus_dram_target_id;  in mvebu_mbus_get_dram_win_info()
950 			*attr = cs->mbus_attr;  in mvebu_mbus_get_dram_win_info()
956 	return -EINVAL;  in mvebu_mbus_get_dram_win_info()
965 	for (win = 0; win < mbus_state.soc->num_wins; win++) {  in mvebu_mbus_get_io_win_info()
979 	return -EINVAL;  in mvebu_mbus_get_io_win_info()
992 	if (!s->mbuswins_base)  in mvebu_mbus_debugfs_init()
995 	s->debugfs_root = debugfs_create_dir("mvebu-mbus", NULL);  in mvebu_mbus_debugfs_init()
996 	if (s->debugfs_root) {  in mvebu_mbus_debugfs_init()
997 		s->debugfs_sdram = debugfs_create_file("sdram", S_IRUGO,  in mvebu_mbus_debugfs_init()
998 						       s->debugfs_root, NULL,  in mvebu_mbus_debugfs_init()
1000 		s->debugfs_devs = debugfs_create_file("devices", S_IRUGO,  in mvebu_mbus_debugfs_init()
1001 						      s->debugfs_root, NULL,  in mvebu_mbus_debugfs_init()
1014 	if (!s->mbusbridge_base)  in mvebu_mbus_suspend()
1015 		return -ENODEV;  in mvebu_mbus_suspend()
1017 	for (win = 0; win < s->soc->num_wins; win++) {  in mvebu_mbus_suspend()
1018 		void __iomem *addr = s->mbuswins_base +  in mvebu_mbus_suspend()
1019 			s->soc->win_cfg_offset(win);  in mvebu_mbus_suspend()
1022 		s->wins[win].base = readl(addr + WIN_BASE_OFF);  in mvebu_mbus_suspend()
1023 		s->wins[win].ctrl = readl(addr + WIN_CTRL_OFF);  in mvebu_mbus_suspend()
1028 		addr_rmp = s->mbuswins_base +  in mvebu_mbus_suspend()
1029 			s->soc->win_remap_offset(win);  in mvebu_mbus_suspend()
1031 		s->wins[win].remap_lo = readl(addr_rmp + WIN_REMAP_LO_OFF);  in mvebu_mbus_suspend()
1032 		s->wins[win].remap_hi = readl(addr_rmp + WIN_REMAP_HI_OFF);  in mvebu_mbus_suspend()
1035 	s->mbus_bridge_ctrl = readl(s->mbusbridge_base +  in mvebu_mbus_suspend()
1037 	s->mbus_bridge_base = readl(s->mbusbridge_base +  in mvebu_mbus_suspend()
1048 	writel(s->mbus_bridge_ctrl,  in mvebu_mbus_resume()
1049 	       s->mbusbridge_base + MBUS_BRIDGE_CTRL_OFF);  in mvebu_mbus_resume()
1050 	writel(s->mbus_bridge_base,  in mvebu_mbus_resume()
1051 	       s->mbusbridge_base + MBUS_BRIDGE_BASE_OFF);  in mvebu_mbus_resume()
1053 	for (win = 0; win < s->soc->num_wins; win++) {  in mvebu_mbus_resume()
1054 		void __iomem *addr = s->mbuswins_base +  in mvebu_mbus_resume()
1055 			s->soc->win_cfg_offset(win);  in mvebu_mbus_resume()
1058 		writel(s->wins[win].base, addr + WIN_BASE_OFF);  in mvebu_mbus_resume()
1059 		writel(s->wins[win].ctrl, addr + WIN_CTRL_OFF);  in mvebu_mbus_resume()
1064 		addr_rmp = s->mbuswins_base +  in mvebu_mbus_resume()
1065 			s->soc->win_remap_offset(win);  in mvebu_mbus_resume()
1067 		writel(s->wins[win].remap_lo, addr_rmp + WIN_REMAP_LO_OFF);  in mvebu_mbus_resume()
1068 		writel(s->wins[win].remap_hi, addr_rmp + WIN_REMAP_HI_OFF);  in mvebu_mbus_resume()
1088 	mbus->mbuswins_base = ioremap(mbuswins_phys_base, mbuswins_size);  in mvebu_mbus_common_init()
1089 	if (!mbus->mbuswins_base)  in mvebu_mbus_common_init()
1090 		return -ENOMEM;  in mvebu_mbus_common_init()
1092 	mbus->sdramwins_base = ioremap(sdramwins_phys_base, sdramwins_size);  in mvebu_mbus_common_init()
1093 	if (!mbus->sdramwins_base) {  in mvebu_mbus_common_init()
1094 		iounmap(mbus->mbuswins_base);  in mvebu_mbus_common_init()
1095 		return -ENOMEM;  in mvebu_mbus_common_init()
1098 	mbus->sdramwins_phys_base = sdramwins_phys_base;  in mvebu_mbus_common_init()
1101 		mbus->mbusbridge_base = ioremap(mbusbridge_phys_base,  in mvebu_mbus_common_init()
1103 		if (!mbus->mbusbridge_base) {  in mvebu_mbus_common_init()
1104 			iounmap(mbus->sdramwins_base);  in mvebu_mbus_common_init()
1105 			iounmap(mbus->mbuswins_base);  in mvebu_mbus_common_init()
1106 			return -ENOMEM;  in mvebu_mbus_common_init()
1109 		mbus->mbusbridge_base = NULL;  in mvebu_mbus_common_init()
1111 	for (win = 0; win < mbus->soc->num_wins; win++)  in mvebu_mbus_common_init()
1114 	mbus->soc->setup_cpu_target(mbus);  in mvebu_mbus_common_init()
1119 		       mbus->mbuswins_base + UNIT_SYNC_BARRIER_OFF);  in mvebu_mbus_common_init()
1133 	for (of_id = of_mvebu_mbus_ids; of_id->compatible[0]; of_id++)  in mvebu_mbus_init()
1134 		if (!strcmp(of_id->compatible, soc))  in mvebu_mbus_init()
1137 	if (!of_id->compatible[0]) {  in mvebu_mbus_init()
1139 		return -ENODEV;  in mvebu_mbus_init()
1142 	mbus_state.soc = of_id->data;  in mvebu_mbus_init()
1154  *  - bits 28 to 31: MBus custom field
1155  *  - bits 24 to 27: window target ID
1156  *  - bits 16 to 23: window attribute ID
1157  *  - bits  0 to 15: unused
1170 		return -EBUSY;  in mbus_dt_setup_win()
1177 		return -ENOMEM;  in mbus_dt_setup_win()
1198 		 * An entry with a non-zero custom field do not  in mbus_dt_setup()
1226 	mem->end = -1;  in mvebu_mbus_get_pcie_resources()
1228 	io->end = -1;  in mvebu_mbus_get_pcie_resources()
1230 	ret = of_property_read_u32_array(np, "pcie-mem-aperture", reg, ARRAY_SIZE(reg));  in mvebu_mbus_get_pcie_resources()
1232 		mem->start = reg[0];  in mvebu_mbus_get_pcie_resources()
1233 		mem->end = mem->start + reg[1] - 1;  in mvebu_mbus_get_pcie_resources()
1234 		mem->flags = IORESOURCE_MEM;  in mvebu_mbus_get_pcie_resources()
1237 	ret = of_property_read_u32_array(np, "pcie-io-aperture", reg, ARRAY_SIZE(reg));  in mvebu_mbus_get_pcie_resources()
1239 		io->start = reg[0];  in mvebu_mbus_get_pcie_resources()
1240 		io->end = io->start + reg[1] - 1;  in mvebu_mbus_get_pcie_resources()
1241 		io->flags = IORESOURCE_IO;  in mvebu_mbus_get_pcie_resources()
1256 		return -ENODEV;  in mvebu_mbus_dt_init()
1259 	mbus_state.soc = of_id->data;  in mvebu_mbus_dt_init()
1264 		return -EINVAL;  in mvebu_mbus_dt_init()
1269 		pr_err("could not find an 'mbus-controller' node\n");  in mvebu_mbus_dt_init()
1270 		return -ENODEV;  in mvebu_mbus_dt_init()
1275 		return -EINVAL;  in mvebu_mbus_dt_init()
1280 		return -EINVAL;  in mvebu_mbus_dt_init()
1291 	if (mbus_state.soc->has_mbus_bridge) {  in mvebu_mbus_dt_init()
1293 			pr_warn(FW_WARN "deprecated mbus-mvebu Device Tree, suspend/resume will not work\n");  in mvebu_mbus_dt_init()
1298 	/* Get optional pcie-{mem,io}-aperture properties */  in mvebu_mbus_dt_init()