7  * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
82 	struct bcma_bus *bus = cc->core->bus;  in bcma_pmu2_pll_init0()  local
86 	switch (bus->chipinfo.id) {  in bcma_pmu2_pll_init0()
110 		bcma_err(bus, "Unknown TGT frequency for xtalfreq %d\n",  in bcma_pmu2_pll_init0()
120 		bcma_debug(bus, "Target TGT frequency already set\n");  in bcma_pmu2_pll_init0()
125 	switch (bus->chipinfo.id) {  in bcma_pmu2_pll_init0()
132 		bcma_wait_value(cc->core, BCMA_CLKCTLST,  in bcma_pmu2_pll_init0()
142 	if (cc->pmu.rev >= 2)  in bcma_pmu2_pll_init0()
150 	struct bcma_bus *bus = cc->core->bus;  in bcma_pmu_pll_init()  local
153 	switch (bus->chipinfo.id) {  in bcma_pmu_pll_init()
164 	struct bcma_bus *bus = cc->core->bus;  in bcma_pmu_resources_init()  local
167 	switch (bus->chipinfo.id) {  in bcma_pmu_resources_init()
192 		bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",  in bcma_pmu_resources_init()
193 			   bus->chipinfo.id);  in bcma_pmu_resources_init()
212 	struct bcma_bus *bus = cc->core->bus;  in bcma_chipco_bcm4331_ext_pa_lines_ctl()  local
218 		if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)  in bcma_chipco_bcm4331_ext_pa_lines_ctl()
220 		else if (bus->chipinfo.rev > 0)  in bcma_chipco_bcm4331_ext_pa_lines_ctl()
232 	struct bcma_bus *bus = cc->core->bus;  in bcma_pmu_workarounds()  local
234 	switch (bus->chipinfo.id) {  in bcma_pmu_workarounds()
255 		if (bus->chipinfo.rev == 0) {  in bcma_pmu_workarounds()
269 		bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",  in bcma_pmu_workarounds()
270 			   bus->chipinfo.id);  in bcma_pmu_workarounds()
276 	struct bcma_bus *bus = cc->core->bus;  in bcma_pmu_early_init()  local
279 	if (cc->core->id.rev >= 35 &&  in bcma_pmu_early_init()
280 	    cc->capabilities_ext & BCMA_CC_CAP_EXT_AOB_PRESENT) {  in bcma_pmu_early_init()
281 		cc->pmu.core = bcma_find_core(bus, BCMA_CORE_PMU);  in bcma_pmu_early_init()
282 		if (!cc->pmu.core)  in bcma_pmu_early_init()
283 			bcma_warn(bus, "Couldn't find expected PMU core");  in bcma_pmu_early_init()
285 	if (!cc->pmu.core)  in bcma_pmu_early_init()
286 		cc->pmu.core = cc->core;  in bcma_pmu_early_init()
289 	cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);  in bcma_pmu_early_init()
291 	bcma_debug(bus, "Found rev %u PMU (capabilities 0x%08X)\n", cc->pmu.rev,  in bcma_pmu_early_init()
297 	if (cc->pmu.rev == 1)  in bcma_pmu_init()
311 	struct bcma_bus *bus = cc->core->bus;  in bcma_pmu_get_alp_clock()  local
313 	switch (bus->chipinfo.id) {  in bcma_pmu_get_alp_clock()
339 		if (cc->status & BCMA_CC_CHIPST_4360_XTAL_40MZ)  in bcma_pmu_get_alp_clock()
344 		bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",  in bcma_pmu_get_alp_clock()
345 			  bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);  in bcma_pmu_get_alp_clock()
356 	struct bcma_bus *bus = cc->core->bus;  in bcma_pmu_pll_clock()  local
362 	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||  in bcma_pmu_pll_clock()
363 	    bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {  in bcma_pmu_pll_clock()
375 	div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &  in bcma_pmu_pll_clock()
419 /* query bus clock frequency for PMU-enabled chipcommon */
422 	struct bcma_bus *bus = cc->core->bus;  in bcma_pmu_get_bus_clock()  local
424 	switch (bus->chipinfo.id) {  in bcma_pmu_get_bus_clock()
444 		bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",  in bcma_pmu_get_bus_clock()
445 			  bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);  in bcma_pmu_get_bus_clock()
451 /* query cpu clock frequency for PMU-enabled chipcommon */
454 	struct bcma_bus *bus = cc->core->bus;  in bcma_pmu_get_cpu_clock()  local
456 	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)  in bcma_pmu_get_cpu_clock()
459 	/* New PMUs can have different clock for bus and CPU */  in bcma_pmu_get_cpu_clock()
460 	if (cc->pmu.rev >= 5) {  in bcma_pmu_get_cpu_clock()
462 		switch (bus->chipinfo.id) {  in bcma_pmu_get_cpu_clock()
482 	/* On old PMUs CPU has the same clock as the bus */  in bcma_pmu_get_cpu_clock()
499 	struct bcma_bus *bus = cc->core->bus;  in bcma_pmu_spuravoid_pllupdate()  local
501 	switch (bus->chipinfo.id) {  in bcma_pmu_spuravoid_pllupdate()
511 		phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||  in bcma_pmu_spuravoid_pllupdate()
512 		       bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||  in bcma_pmu_spuravoid_pllupdate()
513 		       bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;  in bcma_pmu_spuravoid_pllupdate()
662 		bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",  in bcma_pmu_spuravoid_pllupdate()
663 			 bus->chipinfo.id);  in bcma_pmu_spuravoid_pllupdate()