Lines Matching +full:interrupt +full:- +full:map
1 // SPDX-License-Identifier: GPL-2.0
12 #include <linux/interrupt.h>
26 struct regmap *map; member
58 return &data->chip->irqs[irq]; in irq_to_regmap_irq()
63 struct regmap *map = data->map; in regmap_irq_can_bulk_read_status() local
66 * While possible that a user-defined ->get_irq_reg() callback might in regmap_irq_can_bulk_read_status()
70 return data->irq_reg_stride == 1 && map->reg_stride == 1 && in regmap_irq_can_bulk_read_status()
71 data->get_irq_reg == regmap_irq_get_irq_reg_linear && in regmap_irq_can_bulk_read_status()
72 !map->use_single_read; in regmap_irq_can_bulk_read_status()
79 mutex_lock(&d->lock); in regmap_irq_lock()
85 struct regmap *map = d->map; in regmap_irq_sync_unlock() local
90 if (d->chip->runtime_pm) { in regmap_irq_sync_unlock()
91 ret = pm_runtime_get_sync(map->dev); in regmap_irq_sync_unlock()
93 dev_err(map->dev, "IRQ sync failed to resume: %d\n", in regmap_irq_sync_unlock()
97 if (d->clear_status) { in regmap_irq_sync_unlock()
98 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
99 reg = d->get_irq_reg(d, d->chip->status_base, i); in regmap_irq_sync_unlock()
101 ret = regmap_read(map, reg, &val); in regmap_irq_sync_unlock()
103 dev_err(d->map->dev, in regmap_irq_sync_unlock()
104 "Failed to clear the interrupt status bits\n"); in regmap_irq_sync_unlock()
107 d->clear_status = false; in regmap_irq_sync_unlock()
115 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
116 if (d->chip->handle_mask_sync) in regmap_irq_sync_unlock()
117 d->chip->handle_mask_sync(i, d->mask_buf_def[i], in regmap_irq_sync_unlock()
118 d->mask_buf[i], in regmap_irq_sync_unlock()
119 d->chip->irq_drv_data); in regmap_irq_sync_unlock()
121 if (d->chip->mask_base && !d->chip->handle_mask_sync) { in regmap_irq_sync_unlock()
122 reg = d->get_irq_reg(d, d->chip->mask_base, i); in regmap_irq_sync_unlock()
123 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
124 d->mask_buf_def[i], in regmap_irq_sync_unlock()
125 d->mask_buf[i]); in regmap_irq_sync_unlock()
127 dev_err(d->map->dev, "Failed to sync masks in %x\n", reg); in regmap_irq_sync_unlock()
130 if (d->chip->unmask_base && !d->chip->handle_mask_sync) { in regmap_irq_sync_unlock()
131 reg = d->get_irq_reg(d, d->chip->unmask_base, i); in regmap_irq_sync_unlock()
132 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
133 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_irq_sync_unlock()
135 dev_err(d->map->dev, "Failed to sync masks in %x\n", in regmap_irq_sync_unlock()
139 reg = d->get_irq_reg(d, d->chip->wake_base, i); in regmap_irq_sync_unlock()
140 if (d->wake_buf) { in regmap_irq_sync_unlock()
141 if (d->chip->wake_invert) in regmap_irq_sync_unlock()
142 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
143 d->mask_buf_def[i], in regmap_irq_sync_unlock()
144 ~d->wake_buf[i]); in regmap_irq_sync_unlock()
146 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
147 d->mask_buf_def[i], in regmap_irq_sync_unlock()
148 d->wake_buf[i]); in regmap_irq_sync_unlock()
150 dev_err(d->map->dev, in regmap_irq_sync_unlock()
155 if (!d->chip->init_ack_masked) in regmap_irq_sync_unlock()
159 * OR if there is masked interrupt which hasn't been Acked, in regmap_irq_sync_unlock()
162 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) { in regmap_irq_sync_unlock()
163 reg = d->get_irq_reg(d, d->chip->ack_base, i); in regmap_irq_sync_unlock()
166 if (d->chip->ack_invert) in regmap_irq_sync_unlock()
167 ret = regmap_write(map, reg, ~d->mask_buf[i]); in regmap_irq_sync_unlock()
169 ret = regmap_write(map, reg, d->mask_buf[i]); in regmap_irq_sync_unlock()
170 if (d->chip->clear_ack) { in regmap_irq_sync_unlock()
171 if (d->chip->ack_invert && !ret) in regmap_irq_sync_unlock()
172 ret = regmap_write(map, reg, UINT_MAX); in regmap_irq_sync_unlock()
174 ret = regmap_write(map, reg, 0); in regmap_irq_sync_unlock()
177 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_sync_unlock()
182 for (i = 0; i < d->chip->num_config_bases; i++) { in regmap_irq_sync_unlock()
183 for (j = 0; j < d->chip->num_config_regs; j++) { in regmap_irq_sync_unlock()
184 reg = d->get_irq_reg(d, d->chip->config_base[i], j); in regmap_irq_sync_unlock()
185 ret = regmap_write(map, reg, d->config_buf[i][j]); in regmap_irq_sync_unlock()
187 dev_err(d->map->dev, in regmap_irq_sync_unlock()
193 if (d->chip->runtime_pm) in regmap_irq_sync_unlock()
194 pm_runtime_put(map->dev); in regmap_irq_sync_unlock()
197 if (d->wake_count < 0) in regmap_irq_sync_unlock()
198 for (i = d->wake_count; i < 0; i++) in regmap_irq_sync_unlock()
199 disable_irq_wake(d->irq); in regmap_irq_sync_unlock()
200 else if (d->wake_count > 0) in regmap_irq_sync_unlock()
201 for (i = 0; i < d->wake_count; i++) in regmap_irq_sync_unlock()
202 enable_irq_wake(d->irq); in regmap_irq_sync_unlock()
204 d->wake_count = 0; in regmap_irq_sync_unlock()
206 mutex_unlock(&d->lock); in regmap_irq_sync_unlock()
212 struct regmap *map = d->map; in regmap_irq_enable() local
213 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_enable()
214 unsigned int reg = irq_data->reg_offset / map->reg_stride; in regmap_irq_enable()
219 * separate mask bits for each interrupt trigger type, but we want in regmap_irq_enable()
220 * to have a single logical interrupt with a configurable type. in regmap_irq_enable()
222 * If the interrupt we're enabling defines any supported types in regmap_irq_enable()
223 * then instead of using the regular mask bits for this interrupt, in regmap_irq_enable()
227 if (d->chip->type_in_mask && irq_data->type.types_supported) in regmap_irq_enable()
228 mask = d->type_buf[reg] & irq_data->mask; in regmap_irq_enable()
230 mask = irq_data->mask; in regmap_irq_enable()
232 if (d->chip->clear_on_unmask) in regmap_irq_enable()
233 d->clear_status = true; in regmap_irq_enable()
235 d->mask_buf[reg] &= ~mask; in regmap_irq_enable()
241 struct regmap *map = d->map; in regmap_irq_disable() local
242 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_disable()
244 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask; in regmap_irq_disable()
250 struct regmap *map = d->map; in regmap_irq_set_type() local
251 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_type()
253 const struct regmap_irq_type *t = &irq_data->type; in regmap_irq_set_type()
255 if ((t->types_supported & type) != type) in regmap_irq_set_type()
258 reg = t->type_reg_offset / map->reg_stride; in regmap_irq_set_type()
260 if (d->chip->type_in_mask) { in regmap_irq_set_type()
261 ret = regmap_irq_set_type_config_simple(&d->type_buf, type, in regmap_irq_set_type()
262 irq_data, reg, d->chip->irq_drv_data); in regmap_irq_set_type()
267 if (d->chip->set_type_config) { in regmap_irq_set_type()
268 ret = d->chip->set_type_config(d->config_buf, type, irq_data, in regmap_irq_set_type()
269 reg, d->chip->irq_drv_data); in regmap_irq_set_type()
280 struct regmap *map = d->map; in regmap_irq_set_wake() local
281 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_wake()
284 if (d->wake_buf) in regmap_irq_set_wake()
285 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
286 &= ~irq_data->mask; in regmap_irq_set_wake()
287 d->wake_count++; in regmap_irq_set_wake()
289 if (d->wake_buf) in regmap_irq_set_wake()
290 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
291 |= irq_data->mask; in regmap_irq_set_wake()
292 d->wake_count--; in regmap_irq_set_wake()
310 const struct regmap_irq_chip *chip = data->chip; in read_sub_irq_data()
312 struct regmap *map = data->map; in read_sub_irq_data() local
316 if (!chip->sub_reg_offsets) { in read_sub_irq_data()
317 reg = data->get_irq_reg(data, chip->status_base, b); in read_sub_irq_data()
318 ret = regmap_read(map, reg, &data->status_buf[b]); in read_sub_irq_data()
321 * Note we can't use ->get_irq_reg() here because the offsets in read_sub_irq_data()
324 subreg = &chip->sub_reg_offsets[b]; in read_sub_irq_data()
325 for (i = 0; i < subreg->num_regs; i++) { in read_sub_irq_data()
326 unsigned int offset = subreg->offset[i]; in read_sub_irq_data()
327 unsigned int index = offset / map->reg_stride; in read_sub_irq_data()
329 ret = regmap_read(map, chip->status_base + offset, in read_sub_irq_data()
330 &data->status_buf[index]); in read_sub_irq_data()
340 const struct regmap_irq_chip *chip = data->chip; in read_irq_data()
341 struct regmap *map = data->map; in read_irq_data() local
351 if (chip->no_status) { in read_irq_data()
353 memset32(data->status_buf, GENMASK(31, 0), chip->num_regs); in read_irq_data()
354 } else if (chip->num_main_regs) { in read_irq_data()
357 max_main_bits = (chip->num_main_status_bits) ? in read_irq_data()
358 chip->num_main_status_bits : chip->num_regs; in read_irq_data()
360 memset32(data->status_buf, 0, chip->num_regs); in read_irq_data()
367 for (i = 0; i < chip->num_main_regs; i++) { in read_irq_data()
368 reg = data->get_irq_reg(data, chip->main_status, i); in read_irq_data()
369 ret = regmap_read(map, reg, &data->main_status_buf[i]); in read_irq_data()
371 dev_err(map->dev, "Failed to read IRQ status %d\n", ret); in read_irq_data()
377 for (i = 0; i < chip->num_main_regs; i++) { in read_irq_data()
379 const unsigned long mreg = data->main_status_buf[i]; in read_irq_data()
381 for_each_set_bit(b, &mreg, map->format.val_bytes * 8) { in read_irq_data()
382 if (i * map->format.val_bytes * 8 + b > in read_irq_data()
388 dev_err(map->dev, "Failed to read IRQ status %d\n", ret); in read_irq_data()
396 u8 *buf8 = data->status_reg_buf; in read_irq_data()
397 u16 *buf16 = data->status_reg_buf; in read_irq_data()
398 u32 *buf32 = data->status_reg_buf; in read_irq_data()
400 BUG_ON(!data->status_reg_buf); in read_irq_data()
402 ret = regmap_bulk_read(map, chip->status_base, in read_irq_data()
403 data->status_reg_buf, in read_irq_data()
404 chip->num_regs); in read_irq_data()
406 dev_err(map->dev, "Failed to read IRQ status: %d\n", ret); in read_irq_data()
410 for (i = 0; i < data->chip->num_regs; i++) { in read_irq_data()
411 switch (map->format.val_bytes) { in read_irq_data()
413 data->status_buf[i] = buf8[i]; in read_irq_data()
416 data->status_buf[i] = buf16[i]; in read_irq_data()
419 data->status_buf[i] = buf32[i]; in read_irq_data()
423 return -EIO; in read_irq_data()
428 for (i = 0; i < data->chip->num_regs; i++) { in read_irq_data()
429 unsigned int reg = data->get_irq_reg(data, in read_irq_data()
430 data->chip->status_base, i); in read_irq_data()
431 ret = regmap_read(map, reg, &data->status_buf[i]); in read_irq_data()
434 dev_err(map->dev, "Failed to read IRQ status: %d\n", ret); in read_irq_data()
440 if (chip->status_invert) in read_irq_data()
441 for (i = 0; i < data->chip->num_regs; i++) in read_irq_data()
442 data->status_buf[i] = ~data->status_buf[i]; in read_irq_data()
450 const struct regmap_irq_chip *chip = data->chip; in regmap_irq_thread()
451 struct regmap *map = data->map; in regmap_irq_thread() local
456 if (chip->handle_pre_irq) in regmap_irq_thread()
457 chip->handle_pre_irq(chip->irq_drv_data); in regmap_irq_thread()
459 if (chip->runtime_pm) { in regmap_irq_thread()
460 ret = pm_runtime_get_sync(map->dev); in regmap_irq_thread()
462 dev_err(map->dev, "IRQ thread failed to resume: %d\n", ret); in regmap_irq_thread()
471 if (chip->status_is_level) { in regmap_irq_thread()
472 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
473 unsigned int val = data->status_buf[i]; in regmap_irq_thread()
475 data->status_buf[i] ^= data->prev_status_buf[i]; in regmap_irq_thread()
476 data->prev_status_buf[i] = val; in regmap_irq_thread()
483 * interrupt. We assume that typically few of the interrupts in regmap_irq_thread()
487 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
488 data->status_buf[i] &= ~data->mask_buf[i]; in regmap_irq_thread()
490 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_irq_thread()
491 reg = data->get_irq_reg(data, data->chip->ack_base, i); in regmap_irq_thread()
493 if (chip->ack_invert) in regmap_irq_thread()
494 ret = regmap_write(map, reg, in regmap_irq_thread()
495 ~data->status_buf[i]); in regmap_irq_thread()
497 ret = regmap_write(map, reg, in regmap_irq_thread()
498 data->status_buf[i]); in regmap_irq_thread()
499 if (chip->clear_ack) { in regmap_irq_thread()
500 if (chip->ack_invert && !ret) in regmap_irq_thread()
501 ret = regmap_write(map, reg, UINT_MAX); in regmap_irq_thread()
503 ret = regmap_write(map, reg, 0); in regmap_irq_thread()
506 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_thread()
511 for (i = 0; i < chip->num_irqs; i++) { in regmap_irq_thread()
512 if (data->status_buf[chip->irqs[i].reg_offset / in regmap_irq_thread()
513 map->reg_stride] & chip->irqs[i].mask) { in regmap_irq_thread()
514 handle_nested_irq(irq_find_mapping(data->domain, i)); in regmap_irq_thread()
520 if (chip->handle_post_irq) in regmap_irq_thread()
521 chip->handle_post_irq(chip->irq_drv_data); in regmap_irq_thread()
523 if (chip->runtime_pm) in regmap_irq_thread()
524 pm_runtime_put(map->dev); in regmap_irq_thread()
538 struct regmap_irq_chip_data *data = h->host_data; in regmap_irq_map()
542 irq_set_chip(virq, &data->irq_chip); in regmap_irq_map()
544 irq_set_parent(virq, data->irq); in regmap_irq_map()
551 .map = regmap_irq_map,
556 * regmap_irq_get_irq_reg_linear() - Linear IRQ register mapping callback.
567 struct regmap *map = data->map; in regmap_irq_get_irq_reg_linear() local
569 return base + index * map->reg_stride * data->irq_reg_stride; in regmap_irq_get_irq_reg_linear()
574 * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback.
582 * This is a &struct regmap_irq_chip->set_type_config callback suitable for
590 const struct regmap_irq_type *t = &irq_data->type; in regmap_irq_set_type_config_simple()
592 if (t->type_reg_mask) in regmap_irq_set_type_config_simple()
593 buf[0][idx] &= ~t->type_reg_mask; in regmap_irq_set_type_config_simple()
595 buf[0][idx] &= ~(t->type_falling_val | in regmap_irq_set_type_config_simple()
596 t->type_rising_val | in regmap_irq_set_type_config_simple()
597 t->type_level_low_val | in regmap_irq_set_type_config_simple()
598 t->type_level_high_val); in regmap_irq_set_type_config_simple()
602 buf[0][idx] |= t->type_falling_val; in regmap_irq_set_type_config_simple()
606 buf[0][idx] |= t->type_rising_val; in regmap_irq_set_type_config_simple()
610 buf[0][idx] |= (t->type_falling_val | in regmap_irq_set_type_config_simple()
611 t->type_rising_val); in regmap_irq_set_type_config_simple()
615 buf[0][idx] |= t->type_level_high_val; in regmap_irq_set_type_config_simple()
619 buf[0][idx] |= t->type_level_low_val; in regmap_irq_set_type_config_simple()
623 return -EINVAL; in regmap_irq_set_type_config_simple()
636 .size = chip->num_irqs, in regmap_irq_create_domain()
637 .hwirq_max = chip->num_irqs, in regmap_irq_create_domain()
641 .name_suffix = chip->domain_suffix, in regmap_irq_create_domain()
644 d->domain = irq_domain_instantiate(&info); in regmap_irq_create_domain()
645 if (IS_ERR(d->domain)) { in regmap_irq_create_domain()
646 dev_err(d->map->dev, "Failed to create IRQ domain\n"); in regmap_irq_create_domain()
647 return PTR_ERR(d->domain); in regmap_irq_create_domain()
655 * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling
658 * @map: The regmap for the device.
660 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
662 * @chip: Configuration for the interrupt controller.
672 struct regmap *map, int irq, in regmap_add_irq_chip_fwnode() argument
679 int ret = -ENOMEM; in regmap_add_irq_chip_fwnode()
682 if (chip->num_regs <= 0) in regmap_add_irq_chip_fwnode()
683 return -EINVAL; in regmap_add_irq_chip_fwnode()
685 if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack)) in regmap_add_irq_chip_fwnode()
686 return -EINVAL; in regmap_add_irq_chip_fwnode()
688 if (chip->mask_base && chip->unmask_base && !chip->mask_unmask_non_inverted) in regmap_add_irq_chip_fwnode()
689 return -EINVAL; in regmap_add_irq_chip_fwnode()
691 for (i = 0; i < chip->num_irqs; i++) { in regmap_add_irq_chip_fwnode()
692 if (chip->irqs[i].reg_offset % map->reg_stride) in regmap_add_irq_chip_fwnode()
693 return -EINVAL; in regmap_add_irq_chip_fwnode()
694 if (chip->irqs[i].reg_offset / map->reg_stride >= in regmap_add_irq_chip_fwnode()
695 chip->num_regs) in regmap_add_irq_chip_fwnode()
696 return -EINVAL; in regmap_add_irq_chip_fwnode()
700 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0); in regmap_add_irq_chip_fwnode()
702 dev_warn(map->dev, "Failed to allocate IRQs: %d\n", in regmap_add_irq_chip_fwnode()
710 return -ENOMEM; in regmap_add_irq_chip_fwnode()
712 if (chip->num_main_regs) { in regmap_add_irq_chip_fwnode()
713 d->main_status_buf = kcalloc(chip->num_main_regs, in regmap_add_irq_chip_fwnode()
714 sizeof(*d->main_status_buf), in regmap_add_irq_chip_fwnode()
717 if (!d->main_status_buf) in regmap_add_irq_chip_fwnode()
721 d->status_buf = kcalloc(chip->num_regs, sizeof(*d->status_buf), in regmap_add_irq_chip_fwnode()
723 if (!d->status_buf) in regmap_add_irq_chip_fwnode()
726 if (chip->status_is_level) { in regmap_add_irq_chip_fwnode()
727 d->prev_status_buf = kcalloc(chip->num_regs, sizeof(*d->prev_status_buf), in regmap_add_irq_chip_fwnode()
729 if (!d->prev_status_buf) in regmap_add_irq_chip_fwnode()
733 d->mask_buf = kcalloc(chip->num_regs, sizeof(*d->mask_buf), in regmap_add_irq_chip_fwnode()
735 if (!d->mask_buf) in regmap_add_irq_chip_fwnode()
738 d->mask_buf_def = kcalloc(chip->num_regs, sizeof(*d->mask_buf_def), in regmap_add_irq_chip_fwnode()
740 if (!d->mask_buf_def) in regmap_add_irq_chip_fwnode()
743 if (chip->wake_base) { in regmap_add_irq_chip_fwnode()
744 d->wake_buf = kcalloc(chip->num_regs, sizeof(*d->wake_buf), in regmap_add_irq_chip_fwnode()
746 if (!d->wake_buf) in regmap_add_irq_chip_fwnode()
750 if (chip->type_in_mask) { in regmap_add_irq_chip_fwnode()
751 d->type_buf_def = kcalloc(chip->num_regs, in regmap_add_irq_chip_fwnode()
752 sizeof(*d->type_buf_def), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
753 if (!d->type_buf_def) in regmap_add_irq_chip_fwnode()
756 d->type_buf = kcalloc(chip->num_regs, sizeof(*d->type_buf), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
757 if (!d->type_buf) in regmap_add_irq_chip_fwnode()
761 if (chip->num_config_bases && chip->num_config_regs) { in regmap_add_irq_chip_fwnode()
765 d->config_buf = kcalloc(chip->num_config_bases, in regmap_add_irq_chip_fwnode()
766 sizeof(*d->config_buf), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
767 if (!d->config_buf) in regmap_add_irq_chip_fwnode()
770 for (i = 0; i < chip->num_config_bases; i++) { in regmap_add_irq_chip_fwnode()
771 d->config_buf[i] = kcalloc(chip->num_config_regs, in regmap_add_irq_chip_fwnode()
772 sizeof(**d->config_buf), in regmap_add_irq_chip_fwnode()
774 if (!d->config_buf[i]) in regmap_add_irq_chip_fwnode()
779 d->irq_chip = regmap_irq_chip; in regmap_add_irq_chip_fwnode()
780 d->irq_chip.name = chip->name; in regmap_add_irq_chip_fwnode()
781 d->irq = irq; in regmap_add_irq_chip_fwnode()
782 d->map = map; in regmap_add_irq_chip_fwnode()
783 d->chip = chip; in regmap_add_irq_chip_fwnode()
784 d->irq_base = irq_base; in regmap_add_irq_chip_fwnode()
786 if (chip->irq_reg_stride) in regmap_add_irq_chip_fwnode()
787 d->irq_reg_stride = chip->irq_reg_stride; in regmap_add_irq_chip_fwnode()
789 d->irq_reg_stride = 1; in regmap_add_irq_chip_fwnode()
791 if (chip->get_irq_reg) in regmap_add_irq_chip_fwnode()
792 d->get_irq_reg = chip->get_irq_reg; in regmap_add_irq_chip_fwnode()
794 d->get_irq_reg = regmap_irq_get_irq_reg_linear; in regmap_add_irq_chip_fwnode()
797 d->status_reg_buf = kmalloc_array(chip->num_regs, in regmap_add_irq_chip_fwnode()
798 map->format.val_bytes, in regmap_add_irq_chip_fwnode()
800 if (!d->status_reg_buf) in regmap_add_irq_chip_fwnode()
804 mutex_init(&d->lock); in regmap_add_irq_chip_fwnode()
806 for (i = 0; i < chip->num_irqs; i++) in regmap_add_irq_chip_fwnode()
807 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride] in regmap_add_irq_chip_fwnode()
808 |= chip->irqs[i].mask; in regmap_add_irq_chip_fwnode()
811 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
812 d->mask_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
814 if (chip->handle_mask_sync) { in regmap_add_irq_chip_fwnode()
815 ret = chip->handle_mask_sync(i, d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
816 d->mask_buf[i], in regmap_add_irq_chip_fwnode()
817 chip->irq_drv_data); in regmap_add_irq_chip_fwnode()
822 if (chip->mask_base && !chip->handle_mask_sync) { in regmap_add_irq_chip_fwnode()
823 reg = d->get_irq_reg(d, chip->mask_base, i); in regmap_add_irq_chip_fwnode()
824 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
825 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
826 d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
828 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
834 if (chip->unmask_base && !chip->handle_mask_sync) { in regmap_add_irq_chip_fwnode()
835 reg = d->get_irq_reg(d, chip->unmask_base, i); in regmap_add_irq_chip_fwnode()
836 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
837 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
839 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
845 if (!chip->init_ack_masked) in regmap_add_irq_chip_fwnode()
849 if (d->chip->no_status) { in regmap_add_irq_chip_fwnode()
851 d->status_buf[i] = UINT_MAX; in regmap_add_irq_chip_fwnode()
853 reg = d->get_irq_reg(d, d->chip->status_base, i); in regmap_add_irq_chip_fwnode()
854 ret = regmap_read(map, reg, &d->status_buf[i]); in regmap_add_irq_chip_fwnode()
856 dev_err(map->dev, "Failed to read IRQ status: %d\n", in regmap_add_irq_chip_fwnode()
862 if (chip->status_invert) in regmap_add_irq_chip_fwnode()
863 d->status_buf[i] = ~d->status_buf[i]; in regmap_add_irq_chip_fwnode()
865 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_add_irq_chip_fwnode()
866 reg = d->get_irq_reg(d, d->chip->ack_base, i); in regmap_add_irq_chip_fwnode()
867 if (chip->ack_invert) in regmap_add_irq_chip_fwnode()
868 ret = regmap_write(map, reg, in regmap_add_irq_chip_fwnode()
869 ~(d->status_buf[i] & d->mask_buf[i])); in regmap_add_irq_chip_fwnode()
871 ret = regmap_write(map, reg, in regmap_add_irq_chip_fwnode()
872 d->status_buf[i] & d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
873 if (chip->clear_ack) { in regmap_add_irq_chip_fwnode()
874 if (chip->ack_invert && !ret) in regmap_add_irq_chip_fwnode()
875 ret = regmap_write(map, reg, UINT_MAX); in regmap_add_irq_chip_fwnode()
877 ret = regmap_write(map, reg, 0); in regmap_add_irq_chip_fwnode()
880 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
888 if (d->wake_buf) { in regmap_add_irq_chip_fwnode()
889 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
890 d->wake_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
891 reg = d->get_irq_reg(d, d->chip->wake_base, i); in regmap_add_irq_chip_fwnode()
893 if (chip->wake_invert) in regmap_add_irq_chip_fwnode()
894 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
895 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
898 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
899 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
900 d->wake_buf[i]); in regmap_add_irq_chip_fwnode()
902 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
910 if (chip->status_is_level) { in regmap_add_irq_chip_fwnode()
915 memcpy(d->prev_status_buf, d->status_buf, in regmap_add_irq_chip_fwnode()
916 array_size(d->chip->num_regs, sizeof(d->prev_status_buf[0]))); in regmap_add_irq_chip_fwnode()
925 chip->name, d); in regmap_add_irq_chip_fwnode()
927 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n", in regmap_add_irq_chip_fwnode()
928 irq, chip->name, ret); in regmap_add_irq_chip_fwnode()
939 kfree(d->type_buf); in regmap_add_irq_chip_fwnode()
940 kfree(d->type_buf_def); in regmap_add_irq_chip_fwnode()
941 kfree(d->wake_buf); in regmap_add_irq_chip_fwnode()
942 kfree(d->mask_buf_def); in regmap_add_irq_chip_fwnode()
943 kfree(d->mask_buf); in regmap_add_irq_chip_fwnode()
944 kfree(d->main_status_buf); in regmap_add_irq_chip_fwnode()
945 kfree(d->status_buf); in regmap_add_irq_chip_fwnode()
946 kfree(d->prev_status_buf); in regmap_add_irq_chip_fwnode()
947 kfree(d->status_reg_buf); in regmap_add_irq_chip_fwnode()
948 if (d->config_buf) { in regmap_add_irq_chip_fwnode()
949 for (i = 0; i < chip->num_config_bases; i++) in regmap_add_irq_chip_fwnode()
950 kfree(d->config_buf[i]); in regmap_add_irq_chip_fwnode()
951 kfree(d->config_buf); in regmap_add_irq_chip_fwnode()
959 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
961 * @map: The regmap for the device.
963 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
965 * @chip: Configuration for the interrupt controller.
973 int regmap_add_irq_chip(struct regmap *map, int irq, int irq_flags, in regmap_add_irq_chip() argument
977 return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq, in regmap_add_irq_chip()
983 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
1001 for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) { in regmap_del_irq_chip()
1003 if (!d->chip->irqs[hwirq].mask) in regmap_del_irq_chip()
1010 virq = irq_find_mapping(d->domain, hwirq); in regmap_del_irq_chip()
1015 irq_domain_remove(d->domain); in regmap_del_irq_chip()
1016 kfree(d->type_buf); in regmap_del_irq_chip()
1017 kfree(d->type_buf_def); in regmap_del_irq_chip()
1018 kfree(d->wake_buf); in regmap_del_irq_chip()
1019 kfree(d->mask_buf_def); in regmap_del_irq_chip()
1020 kfree(d->mask_buf); in regmap_del_irq_chip()
1021 kfree(d->main_status_buf); in regmap_del_irq_chip()
1022 kfree(d->status_reg_buf); in regmap_del_irq_chip()
1023 kfree(d->status_buf); in regmap_del_irq_chip()
1024 kfree(d->prev_status_buf); in regmap_del_irq_chip()
1025 if (d->config_buf) { in regmap_del_irq_chip()
1026 for (i = 0; i < d->chip->num_config_bases; i++) in regmap_del_irq_chip()
1027 kfree(d->config_buf[i]); in regmap_del_irq_chip()
1028 kfree(d->config_buf); in regmap_del_irq_chip()
1038 regmap_del_irq_chip(d->irq, d); in devm_regmap_irq_chip_release()
1054 * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode()
1058 * @map: The regmap for the device.
1060 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
1062 * @chip: Configuration for the interrupt controller.
1072 struct regmap *map, int irq, in devm_regmap_add_irq_chip_fwnode() argument
1083 return -ENOMEM; in devm_regmap_add_irq_chip_fwnode()
1085 ret = regmap_add_irq_chip_fwnode(fwnode, map, irq, irq_flags, irq_base, in devm_regmap_add_irq_chip_fwnode()
1100 * devm_regmap_add_irq_chip() - Resource managed regmap_add_irq_chip()
1103 * @map: The regmap for the device.
1105 * @irq_flags: The IRQF_ flags to use for the primary interrupt.
1107 * @chip: Configuration for the interrupt controller.
1115 int devm_regmap_add_irq_chip(struct device *dev, struct regmap *map, int irq, in devm_regmap_add_irq_chip() argument
1120 return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map, in devm_regmap_add_irq_chip()
1127 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
1140 WARN_ON(irq != data->irq); in devm_regmap_del_irq_chip()
1150 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
1158 WARN_ON(!data->irq_base); in regmap_irq_chip_get_base()
1159 return data->irq_base; in regmap_irq_chip_get_base()
1164 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
1167 * @irq: index of the interrupt requested in the chip IRQs.
1174 if (!data->chip->irqs[irq].mask) in regmap_irq_get_virq()
1175 return -EINVAL; in regmap_irq_get_virq()
1177 return irq_create_mapping(data->domain, irq); in regmap_irq_get_virq()
1182 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
1194 return data->domain; in regmap_irq_get_domain()