Lines Matching +full:d +full:-
1 // SPDX-License-Identifier: GPL-2.0
59 return &data->chip->irqs[irq]; in irq_to_regmap_irq()
64 struct regmap *map = data->map; in regmap_irq_can_bulk_read_status()
67 * While possible that a user-defined ->get_irq_reg() callback might in regmap_irq_can_bulk_read_status()
71 return data->irq_reg_stride == 1 && map->reg_stride == 1 && in regmap_irq_can_bulk_read_status()
72 data->get_irq_reg == regmap_irq_get_irq_reg_linear && in regmap_irq_can_bulk_read_status()
73 !map->use_single_read; in regmap_irq_can_bulk_read_status()
78 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); in regmap_irq_lock() local
80 mutex_lock(&d->lock); in regmap_irq_lock()
85 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); in regmap_irq_sync_unlock() local
86 struct regmap *map = d->map; in regmap_irq_sync_unlock()
91 if (d->chip->runtime_pm) { in regmap_irq_sync_unlock()
92 ret = pm_runtime_get_sync(map->dev); in regmap_irq_sync_unlock()
94 dev_err(map->dev, "IRQ sync failed to resume: %d\n", in regmap_irq_sync_unlock()
98 if (d->clear_status) { in regmap_irq_sync_unlock()
99 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
100 reg = d->get_irq_reg(d, d->chip->status_base, i); in regmap_irq_sync_unlock()
104 dev_err(d->map->dev, in regmap_irq_sync_unlock()
108 d->clear_status = false; in regmap_irq_sync_unlock()
116 for (i = 0; i < d->chip->num_regs; i++) { in regmap_irq_sync_unlock()
117 if (d->chip->handle_mask_sync) in regmap_irq_sync_unlock()
118 d->chip->handle_mask_sync(i, d->mask_buf_def[i], in regmap_irq_sync_unlock()
119 d->mask_buf[i], in regmap_irq_sync_unlock()
120 d->chip->irq_drv_data); in regmap_irq_sync_unlock()
122 if (d->chip->mask_base && !d->chip->handle_mask_sync) { in regmap_irq_sync_unlock()
123 reg = d->get_irq_reg(d, d->chip->mask_base, i); in regmap_irq_sync_unlock()
124 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
125 d->mask_buf_def[i], in regmap_irq_sync_unlock()
126 d->mask_buf[i]); in regmap_irq_sync_unlock()
128 dev_err(d->map->dev, "Failed to sync masks in %x\n", reg); in regmap_irq_sync_unlock()
131 if (d->chip->unmask_base && !d->chip->handle_mask_sync) { in regmap_irq_sync_unlock()
132 reg = d->get_irq_reg(d, d->chip->unmask_base, i); in regmap_irq_sync_unlock()
133 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
134 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_irq_sync_unlock()
136 dev_err(d->map->dev, "Failed to sync masks in %x\n", in regmap_irq_sync_unlock()
140 reg = d->get_irq_reg(d, d->chip->wake_base, i); in regmap_irq_sync_unlock()
141 if (d->wake_buf) { in regmap_irq_sync_unlock()
142 if (d->chip->wake_invert) in regmap_irq_sync_unlock()
143 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
144 d->mask_buf_def[i], in regmap_irq_sync_unlock()
145 ~d->wake_buf[i]); in regmap_irq_sync_unlock()
147 ret = regmap_update_bits(d->map, reg, in regmap_irq_sync_unlock()
148 d->mask_buf_def[i], in regmap_irq_sync_unlock()
149 d->wake_buf[i]); in regmap_irq_sync_unlock()
151 dev_err(d->map->dev, in regmap_irq_sync_unlock()
152 "Failed to sync wakes in %x: %d\n", in regmap_irq_sync_unlock()
156 if (!d->chip->init_ack_masked) in regmap_irq_sync_unlock()
163 if (d->mask_buf[i] && (d->chip->ack_base || d->chip->use_ack)) { in regmap_irq_sync_unlock()
164 reg = d->get_irq_reg(d, d->chip->ack_base, i); in regmap_irq_sync_unlock()
167 if (d->chip->ack_invert) in regmap_irq_sync_unlock()
168 ret = regmap_write(map, reg, ~d->mask_buf[i]); in regmap_irq_sync_unlock()
170 ret = regmap_write(map, reg, d->mask_buf[i]); in regmap_irq_sync_unlock()
171 if (d->chip->clear_ack) { in regmap_irq_sync_unlock()
172 if (d->chip->ack_invert && !ret) in regmap_irq_sync_unlock()
178 dev_err(d->map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_sync_unlock()
183 for (i = 0; i < d->chip->num_config_bases; i++) { in regmap_irq_sync_unlock()
184 for (j = 0; j < d->chip->num_config_regs; j++) { in regmap_irq_sync_unlock()
185 reg = d->get_irq_reg(d, d->chip->config_base[i], j); in regmap_irq_sync_unlock()
186 ret = regmap_write(map, reg, d->config_buf[i][j]); in regmap_irq_sync_unlock()
188 dev_err(d->map->dev, in regmap_irq_sync_unlock()
189 "Failed to write config %x: %d\n", in regmap_irq_sync_unlock()
194 if (d->chip->runtime_pm) in regmap_irq_sync_unlock()
195 pm_runtime_put(map->dev); in regmap_irq_sync_unlock()
198 if (d->wake_count < 0) in regmap_irq_sync_unlock()
199 for (i = d->wake_count; i < 0; i++) in regmap_irq_sync_unlock()
200 disable_irq_wake(d->irq); in regmap_irq_sync_unlock()
201 else if (d->wake_count > 0) in regmap_irq_sync_unlock()
202 for (i = 0; i < d->wake_count; i++) in regmap_irq_sync_unlock()
203 enable_irq_wake(d->irq); in regmap_irq_sync_unlock()
205 d->wake_count = 0; in regmap_irq_sync_unlock()
207 mutex_unlock(&d->lock); in regmap_irq_sync_unlock()
212 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); in regmap_irq_enable() local
213 struct regmap *map = d->map; in regmap_irq_enable()
214 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_enable()
215 unsigned int reg = irq_data->reg_offset / map->reg_stride; in regmap_irq_enable()
228 if (d->chip->type_in_mask && irq_data->type.types_supported) in regmap_irq_enable()
229 mask = d->type_buf[reg] & irq_data->mask; in regmap_irq_enable()
231 mask = irq_data->mask; in regmap_irq_enable()
233 if (d->chip->clear_on_unmask) in regmap_irq_enable()
234 d->clear_status = true; in regmap_irq_enable()
236 d->mask_buf[reg] &= ~mask; in regmap_irq_enable()
241 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); in regmap_irq_disable() local
242 struct regmap *map = d->map; in regmap_irq_disable()
243 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_disable()
245 d->mask_buf[irq_data->reg_offset / map->reg_stride] |= irq_data->mask; in regmap_irq_disable()
250 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); in regmap_irq_set_type() local
251 struct regmap *map = d->map; in regmap_irq_set_type()
252 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_type()
254 const struct regmap_irq_type *t = &irq_data->type; in regmap_irq_set_type()
256 if ((t->types_supported & type) != type) in regmap_irq_set_type()
259 reg = t->type_reg_offset / map->reg_stride; in regmap_irq_set_type()
261 if (d->chip->type_in_mask) { in regmap_irq_set_type()
262 ret = regmap_irq_set_type_config_simple(&d->type_buf, type, in regmap_irq_set_type()
263 irq_data, reg, d->chip->irq_drv_data); in regmap_irq_set_type()
268 if (d->chip->set_type_config) { in regmap_irq_set_type()
269 ret = d->chip->set_type_config(d->config_buf, type, irq_data, in regmap_irq_set_type()
270 reg, d->chip->irq_drv_data); in regmap_irq_set_type()
280 struct regmap_irq_chip_data *d = irq_data_get_irq_chip_data(data); in regmap_irq_set_wake() local
281 struct regmap *map = d->map; in regmap_irq_set_wake()
282 const struct regmap_irq *irq_data = irq_to_regmap_irq(d, data->hwirq); in regmap_irq_set_wake()
285 if (d->wake_buf) in regmap_irq_set_wake()
286 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
287 &= ~irq_data->mask; in regmap_irq_set_wake()
288 d->wake_count++; in regmap_irq_set_wake()
290 if (d->wake_buf) in regmap_irq_set_wake()
291 d->wake_buf[irq_data->reg_offset / map->reg_stride] in regmap_irq_set_wake()
292 |= irq_data->mask; in regmap_irq_set_wake()
293 d->wake_count--; in regmap_irq_set_wake()
311 const struct regmap_irq_chip *chip = data->chip; in read_sub_irq_data()
313 struct regmap *map = data->map; in read_sub_irq_data()
317 if (!chip->sub_reg_offsets) { in read_sub_irq_data()
318 reg = data->get_irq_reg(data, chip->status_base, b); in read_sub_irq_data()
319 ret = regmap_read(map, reg, &data->status_buf[b]); in read_sub_irq_data()
322 * Note we can't use ->get_irq_reg() here because the offsets in read_sub_irq_data()
325 subreg = &chip->sub_reg_offsets[b]; in read_sub_irq_data()
326 for (i = 0; i < subreg->num_regs; i++) { in read_sub_irq_data()
327 unsigned int offset = subreg->offset[i]; in read_sub_irq_data()
328 unsigned int index = offset / map->reg_stride; in read_sub_irq_data()
330 ret = regmap_read(map, chip->status_base + offset, in read_sub_irq_data()
331 &data->status_buf[index]); in read_sub_irq_data()
341 const struct regmap_irq_chip *chip = data->chip; in read_irq_data()
342 struct regmap *map = data->map; in read_irq_data()
352 if (chip->no_status) { in read_irq_data()
354 memset32(data->status_buf, GENMASK(31, 0), chip->num_regs); in read_irq_data()
355 } else if (chip->num_main_regs) { in read_irq_data()
358 max_main_bits = (chip->num_main_status_bits) ? in read_irq_data()
359 chip->num_main_status_bits : chip->num_regs; in read_irq_data()
361 memset32(data->status_buf, 0, chip->num_regs); in read_irq_data()
368 for (i = 0; i < chip->num_main_regs; i++) { in read_irq_data()
369 reg = data->get_irq_reg(data, chip->main_status, i); in read_irq_data()
370 ret = regmap_read(map, reg, &data->main_status_buf[i]); in read_irq_data()
372 dev_err(map->dev, "Failed to read IRQ status %d\n", ret); in read_irq_data()
378 for (i = 0; i < chip->num_main_regs; i++) { in read_irq_data()
380 const unsigned long mreg = data->main_status_buf[i]; in read_irq_data()
382 for_each_set_bit(b, &mreg, map->format.val_bytes * 8) { in read_irq_data()
383 if (i * map->format.val_bytes * 8 + b > in read_irq_data()
389 dev_err(map->dev, "Failed to read IRQ status %d\n", ret); in read_irq_data()
397 u8 *buf8 = data->status_reg_buf; in read_irq_data()
398 u16 *buf16 = data->status_reg_buf; in read_irq_data()
399 u32 *buf32 = data->status_reg_buf; in read_irq_data()
401 BUG_ON(!data->status_reg_buf); in read_irq_data()
403 ret = regmap_bulk_read(map, chip->status_base, in read_irq_data()
404 data->status_reg_buf, in read_irq_data()
405 chip->num_regs); in read_irq_data()
407 dev_err(map->dev, "Failed to read IRQ status: %d\n", ret); in read_irq_data()
411 for (i = 0; i < data->chip->num_regs; i++) { in read_irq_data()
412 switch (map->format.val_bytes) { in read_irq_data()
414 data->status_buf[i] = buf8[i]; in read_irq_data()
417 data->status_buf[i] = buf16[i]; in read_irq_data()
420 data->status_buf[i] = buf32[i]; in read_irq_data()
424 return -EIO; in read_irq_data()
429 for (i = 0; i < data->chip->num_regs; i++) { in read_irq_data()
430 unsigned int reg = data->get_irq_reg(data, in read_irq_data()
431 data->chip->status_base, i); in read_irq_data()
432 ret = regmap_read(map, reg, &data->status_buf[i]); in read_irq_data()
435 dev_err(map->dev, "Failed to read IRQ status: %d\n", ret); in read_irq_data()
441 if (chip->status_invert) in read_irq_data()
442 for (i = 0; i < data->chip->num_regs; i++) in read_irq_data()
443 data->status_buf[i] = ~data->status_buf[i]; in read_irq_data()
448 static irqreturn_t regmap_irq_thread(int irq, void *d) in regmap_irq_thread() argument
450 struct regmap_irq_chip_data *data = d; in regmap_irq_thread()
451 const struct regmap_irq_chip *chip = data->chip; in regmap_irq_thread()
452 struct regmap *map = data->map; in regmap_irq_thread()
457 if (chip->handle_pre_irq) in regmap_irq_thread()
458 chip->handle_pre_irq(chip->irq_drv_data); in regmap_irq_thread()
460 if (chip->runtime_pm) { in regmap_irq_thread()
461 ret = pm_runtime_get_sync(map->dev); in regmap_irq_thread()
463 dev_err(map->dev, "IRQ thread failed to resume: %d\n", ret); in regmap_irq_thread()
472 if (chip->status_is_level) { in regmap_irq_thread()
473 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
474 unsigned int val = data->status_buf[i]; in regmap_irq_thread()
476 data->status_buf[i] ^= data->prev_status_buf[i]; in regmap_irq_thread()
477 data->prev_status_buf[i] = val; in regmap_irq_thread()
488 for (i = 0; i < data->chip->num_regs; i++) { in regmap_irq_thread()
489 data->status_buf[i] &= ~data->mask_buf[i]; in regmap_irq_thread()
491 if (data->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_irq_thread()
492 reg = data->get_irq_reg(data, data->chip->ack_base, i); in regmap_irq_thread()
494 if (chip->ack_invert) in regmap_irq_thread()
496 ~data->status_buf[i]); in regmap_irq_thread()
499 data->status_buf[i]); in regmap_irq_thread()
500 if (chip->clear_ack) { in regmap_irq_thread()
501 if (chip->ack_invert && !ret) in regmap_irq_thread()
507 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_irq_thread()
512 for (i = 0; i < chip->num_irqs; i++) { in regmap_irq_thread()
513 if (data->status_buf[chip->irqs[i].reg_offset / in regmap_irq_thread()
514 map->reg_stride] & chip->irqs[i].mask) { in regmap_irq_thread()
515 handle_nested_irq(irq_find_mapping(data->domain, i)); in regmap_irq_thread()
521 if (chip->handle_post_irq) in regmap_irq_thread()
522 chip->handle_post_irq(chip->irq_drv_data); in regmap_irq_thread()
524 if (chip->runtime_pm) in regmap_irq_thread()
525 pm_runtime_put(map->dev); in regmap_irq_thread()
539 struct regmap_irq_chip_data *data = h->host_data; in regmap_irq_map()
543 irq_set_chip(virq, &data->irq_chip); in regmap_irq_map()
545 irq_set_parent(virq, data->irq); in regmap_irq_map()
557 * regmap_irq_get_irq_reg_linear() - Linear IRQ register mapping callback.
568 struct regmap *map = data->map; in regmap_irq_get_irq_reg_linear()
570 return base + index * map->reg_stride * data->irq_reg_stride; in regmap_irq_get_irq_reg_linear()
575 * regmap_irq_set_type_config_simple() - Simple IRQ type configuration callback.
576 * @buf: Buffer containing configuration register values, this is a 2D array of
583 * This is a &struct regmap_irq_chip->set_type_config callback suitable for
591 const struct regmap_irq_type *t = &irq_data->type; in regmap_irq_set_type_config_simple()
593 if (t->type_reg_mask) in regmap_irq_set_type_config_simple()
594 buf[0][idx] &= ~t->type_reg_mask; in regmap_irq_set_type_config_simple()
596 buf[0][idx] &= ~(t->type_falling_val | in regmap_irq_set_type_config_simple()
597 t->type_rising_val | in regmap_irq_set_type_config_simple()
598 t->type_level_low_val | in regmap_irq_set_type_config_simple()
599 t->type_level_high_val); in regmap_irq_set_type_config_simple()
603 buf[0][idx] |= t->type_falling_val; in regmap_irq_set_type_config_simple()
607 buf[0][idx] |= t->type_rising_val; in regmap_irq_set_type_config_simple()
611 buf[0][idx] |= (t->type_falling_val | in regmap_irq_set_type_config_simple()
612 t->type_rising_val); in regmap_irq_set_type_config_simple()
616 buf[0][idx] |= t->type_level_high_val; in regmap_irq_set_type_config_simple()
620 buf[0][idx] |= t->type_level_low_val; in regmap_irq_set_type_config_simple()
624 return -EINVAL; in regmap_irq_set_type_config_simple()
633 struct regmap_irq_chip_data *d) in regmap_irq_create_domain() argument
637 .size = chip->num_irqs, in regmap_irq_create_domain()
638 .hwirq_max = chip->num_irqs, in regmap_irq_create_domain()
641 .host_data = d, in regmap_irq_create_domain()
642 .name_suffix = chip->domain_suffix, in regmap_irq_create_domain()
645 d->domain = irq_domain_instantiate(&info); in regmap_irq_create_domain()
646 if (IS_ERR(d->domain)) { in regmap_irq_create_domain()
647 dev_err(d->map->dev, "Failed to create IRQ domain\n"); in regmap_irq_create_domain()
648 return PTR_ERR(d->domain); in regmap_irq_create_domain()
656 * regmap_add_irq_chip_fwnode() - Use standard regmap IRQ controller handling
678 struct regmap_irq_chip_data *d; in regmap_add_irq_chip_fwnode() local
680 int ret = -ENOMEM; in regmap_add_irq_chip_fwnode()
683 if (chip->num_regs <= 0) in regmap_add_irq_chip_fwnode()
684 return -EINVAL; in regmap_add_irq_chip_fwnode()
686 if (chip->clear_on_unmask && (chip->ack_base || chip->use_ack)) in regmap_add_irq_chip_fwnode()
687 return -EINVAL; in regmap_add_irq_chip_fwnode()
689 if (chip->mask_base && chip->unmask_base && !chip->mask_unmask_non_inverted) in regmap_add_irq_chip_fwnode()
690 return -EINVAL; in regmap_add_irq_chip_fwnode()
692 for (i = 0; i < chip->num_irqs; i++) { in regmap_add_irq_chip_fwnode()
693 if (chip->irqs[i].reg_offset % map->reg_stride) in regmap_add_irq_chip_fwnode()
694 return -EINVAL; in regmap_add_irq_chip_fwnode()
695 if (chip->irqs[i].reg_offset / map->reg_stride >= in regmap_add_irq_chip_fwnode()
696 chip->num_regs) in regmap_add_irq_chip_fwnode()
697 return -EINVAL; in regmap_add_irq_chip_fwnode()
701 irq_base = irq_alloc_descs(irq_base, 0, chip->num_irqs, 0); in regmap_add_irq_chip_fwnode()
703 dev_warn(map->dev, "Failed to allocate IRQs: %d\n", in regmap_add_irq_chip_fwnode()
709 d = kzalloc(sizeof(*d), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
710 if (!d) in regmap_add_irq_chip_fwnode()
711 return -ENOMEM; in regmap_add_irq_chip_fwnode()
713 if (chip->num_main_regs) { in regmap_add_irq_chip_fwnode()
714 d->main_status_buf = kcalloc(chip->num_main_regs, in regmap_add_irq_chip_fwnode()
715 sizeof(*d->main_status_buf), in regmap_add_irq_chip_fwnode()
718 if (!d->main_status_buf) in regmap_add_irq_chip_fwnode()
722 d->status_buf = kcalloc(chip->num_regs, sizeof(*d->status_buf), in regmap_add_irq_chip_fwnode()
724 if (!d->status_buf) in regmap_add_irq_chip_fwnode()
727 if (chip->status_is_level) { in regmap_add_irq_chip_fwnode()
728 d->prev_status_buf = kcalloc(chip->num_regs, sizeof(*d->prev_status_buf), in regmap_add_irq_chip_fwnode()
730 if (!d->prev_status_buf) in regmap_add_irq_chip_fwnode()
734 d->mask_buf = kcalloc(chip->num_regs, sizeof(*d->mask_buf), in regmap_add_irq_chip_fwnode()
736 if (!d->mask_buf) in regmap_add_irq_chip_fwnode()
739 d->mask_buf_def = kcalloc(chip->num_regs, sizeof(*d->mask_buf_def), in regmap_add_irq_chip_fwnode()
741 if (!d->mask_buf_def) in regmap_add_irq_chip_fwnode()
744 if (chip->wake_base) { in regmap_add_irq_chip_fwnode()
745 d->wake_buf = kcalloc(chip->num_regs, sizeof(*d->wake_buf), in regmap_add_irq_chip_fwnode()
747 if (!d->wake_buf) in regmap_add_irq_chip_fwnode()
751 if (chip->type_in_mask) { in regmap_add_irq_chip_fwnode()
752 d->type_buf_def = kcalloc(chip->num_regs, in regmap_add_irq_chip_fwnode()
753 sizeof(*d->type_buf_def), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
754 if (!d->type_buf_def) in regmap_add_irq_chip_fwnode()
757 d->type_buf = kcalloc(chip->num_regs, sizeof(*d->type_buf), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
758 if (!d->type_buf) in regmap_add_irq_chip_fwnode()
762 if (chip->num_config_bases && chip->num_config_regs) { in regmap_add_irq_chip_fwnode()
766 d->config_buf = kcalloc(chip->num_config_bases, in regmap_add_irq_chip_fwnode()
767 sizeof(*d->config_buf), GFP_KERNEL); in regmap_add_irq_chip_fwnode()
768 if (!d->config_buf) in regmap_add_irq_chip_fwnode()
771 for (i = 0; i < chip->num_config_bases; i++) { in regmap_add_irq_chip_fwnode()
772 d->config_buf[i] = kcalloc(chip->num_config_regs, in regmap_add_irq_chip_fwnode()
773 sizeof(**d->config_buf), in regmap_add_irq_chip_fwnode()
775 if (!d->config_buf[i]) in regmap_add_irq_chip_fwnode()
780 d->irq_chip = regmap_irq_chip; in regmap_add_irq_chip_fwnode()
781 d->irq_chip.name = chip->name; in regmap_add_irq_chip_fwnode()
782 d->irq = irq; in regmap_add_irq_chip_fwnode()
783 d->map = map; in regmap_add_irq_chip_fwnode()
784 d->chip = chip; in regmap_add_irq_chip_fwnode()
785 d->irq_base = irq_base; in regmap_add_irq_chip_fwnode()
787 if (chip->irq_reg_stride) in regmap_add_irq_chip_fwnode()
788 d->irq_reg_stride = chip->irq_reg_stride; in regmap_add_irq_chip_fwnode()
790 d->irq_reg_stride = 1; in regmap_add_irq_chip_fwnode()
792 if (chip->get_irq_reg) in regmap_add_irq_chip_fwnode()
793 d->get_irq_reg = chip->get_irq_reg; in regmap_add_irq_chip_fwnode()
795 d->get_irq_reg = regmap_irq_get_irq_reg_linear; in regmap_add_irq_chip_fwnode()
797 if (regmap_irq_can_bulk_read_status(d)) { in regmap_add_irq_chip_fwnode()
798 d->status_reg_buf = kmalloc_array(chip->num_regs, in regmap_add_irq_chip_fwnode()
799 map->format.val_bytes, in regmap_add_irq_chip_fwnode()
801 if (!d->status_reg_buf) in regmap_add_irq_chip_fwnode()
806 * If one regmap-irq is the parent of another then we'll try in regmap_add_irq_chip_fwnode()
810 lockdep_register_key(&d->lock_key); in regmap_add_irq_chip_fwnode()
811 mutex_init_with_key(&d->lock, &d->lock_key); in regmap_add_irq_chip_fwnode()
813 for (i = 0; i < chip->num_irqs; i++) in regmap_add_irq_chip_fwnode()
814 d->mask_buf_def[chip->irqs[i].reg_offset / map->reg_stride] in regmap_add_irq_chip_fwnode()
815 |= chip->irqs[i].mask; in regmap_add_irq_chip_fwnode()
818 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
819 d->mask_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
821 if (chip->handle_mask_sync) { in regmap_add_irq_chip_fwnode()
822 ret = chip->handle_mask_sync(i, d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
823 d->mask_buf[i], in regmap_add_irq_chip_fwnode()
824 chip->irq_drv_data); in regmap_add_irq_chip_fwnode()
829 if (chip->mask_base && !chip->handle_mask_sync) { in regmap_add_irq_chip_fwnode()
830 reg = d->get_irq_reg(d, chip->mask_base, i); in regmap_add_irq_chip_fwnode()
831 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
832 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
833 d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
835 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
841 if (chip->unmask_base && !chip->handle_mask_sync) { in regmap_add_irq_chip_fwnode()
842 reg = d->get_irq_reg(d, chip->unmask_base, i); in regmap_add_irq_chip_fwnode()
843 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
844 d->mask_buf_def[i], ~d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
846 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
852 if (!chip->init_ack_masked) in regmap_add_irq_chip_fwnode()
856 if (d->chip->no_status) { in regmap_add_irq_chip_fwnode()
858 d->status_buf[i] = UINT_MAX; in regmap_add_irq_chip_fwnode()
860 reg = d->get_irq_reg(d, d->chip->status_base, i); in regmap_add_irq_chip_fwnode()
861 ret = regmap_read(map, reg, &d->status_buf[i]); in regmap_add_irq_chip_fwnode()
863 dev_err(map->dev, "Failed to read IRQ status: %d\n", in regmap_add_irq_chip_fwnode()
869 if (chip->status_invert) in regmap_add_irq_chip_fwnode()
870 d->status_buf[i] = ~d->status_buf[i]; in regmap_add_irq_chip_fwnode()
872 if (d->status_buf[i] && (chip->ack_base || chip->use_ack)) { in regmap_add_irq_chip_fwnode()
873 reg = d->get_irq_reg(d, d->chip->ack_base, i); in regmap_add_irq_chip_fwnode()
874 if (chip->ack_invert) in regmap_add_irq_chip_fwnode()
876 ~(d->status_buf[i] & d->mask_buf[i])); in regmap_add_irq_chip_fwnode()
879 d->status_buf[i] & d->mask_buf[i]); in regmap_add_irq_chip_fwnode()
880 if (chip->clear_ack) { in regmap_add_irq_chip_fwnode()
881 if (chip->ack_invert && !ret) in regmap_add_irq_chip_fwnode()
887 dev_err(map->dev, "Failed to ack 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
895 if (d->wake_buf) { in regmap_add_irq_chip_fwnode()
896 for (i = 0; i < chip->num_regs; i++) { in regmap_add_irq_chip_fwnode()
897 d->wake_buf[i] = d->mask_buf_def[i]; in regmap_add_irq_chip_fwnode()
898 reg = d->get_irq_reg(d, d->chip->wake_base, i); in regmap_add_irq_chip_fwnode()
900 if (chip->wake_invert) in regmap_add_irq_chip_fwnode()
901 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
902 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
905 ret = regmap_update_bits(d->map, reg, in regmap_add_irq_chip_fwnode()
906 d->mask_buf_def[i], in regmap_add_irq_chip_fwnode()
907 d->wake_buf[i]); in regmap_add_irq_chip_fwnode()
909 dev_err(map->dev, "Failed to set masks in 0x%x: %d\n", in regmap_add_irq_chip_fwnode()
917 if (chip->status_is_level) { in regmap_add_irq_chip_fwnode()
918 ret = read_irq_data(d); in regmap_add_irq_chip_fwnode()
922 memcpy(d->prev_status_buf, d->status_buf, in regmap_add_irq_chip_fwnode()
923 array_size(d->chip->num_regs, sizeof(d->prev_status_buf[0]))); in regmap_add_irq_chip_fwnode()
926 ret = regmap_irq_create_domain(fwnode, irq_base, chip, d); in regmap_add_irq_chip_fwnode()
932 chip->name, d); in regmap_add_irq_chip_fwnode()
934 dev_err(map->dev, "Failed to request IRQ %d for %s: %d\n", in regmap_add_irq_chip_fwnode()
935 irq, chip->name, ret); in regmap_add_irq_chip_fwnode()
939 *data = d; in regmap_add_irq_chip_fwnode()
946 mutex_destroy(&d->lock); in regmap_add_irq_chip_fwnode()
947 lockdep_unregister_key(&d->lock_key); in regmap_add_irq_chip_fwnode()
949 kfree(d->type_buf); in regmap_add_irq_chip_fwnode()
950 kfree(d->type_buf_def); in regmap_add_irq_chip_fwnode()
951 kfree(d->wake_buf); in regmap_add_irq_chip_fwnode()
952 kfree(d->mask_buf_def); in regmap_add_irq_chip_fwnode()
953 kfree(d->mask_buf); in regmap_add_irq_chip_fwnode()
954 kfree(d->main_status_buf); in regmap_add_irq_chip_fwnode()
955 kfree(d->status_buf); in regmap_add_irq_chip_fwnode()
956 kfree(d->prev_status_buf); in regmap_add_irq_chip_fwnode()
957 kfree(d->status_reg_buf); in regmap_add_irq_chip_fwnode()
958 if (d->config_buf) { in regmap_add_irq_chip_fwnode()
959 for (i = 0; i < chip->num_config_bases; i++) in regmap_add_irq_chip_fwnode()
960 kfree(d->config_buf[i]); in regmap_add_irq_chip_fwnode()
961 kfree(d->config_buf); in regmap_add_irq_chip_fwnode()
963 kfree(d); in regmap_add_irq_chip_fwnode()
969 * regmap_add_irq_chip() - Use standard regmap IRQ controller handling
987 return regmap_add_irq_chip_fwnode(dev_fwnode(map->dev), map, irq, in regmap_add_irq_chip()
993 * regmap_del_irq_chip() - Stop interrupt handling for a regmap IRQ chip
996 * @d: ®map_irq_chip_data allocated by regmap_add_irq_chip()
1000 void regmap_del_irq_chip(int irq, struct regmap_irq_chip_data *d) in regmap_del_irq_chip() argument
1005 if (!d) in regmap_del_irq_chip()
1008 free_irq(irq, d); in regmap_del_irq_chip()
1011 for (hwirq = 0; hwirq < d->chip->num_irqs; hwirq++) { in regmap_del_irq_chip()
1013 if (!d->chip->irqs[hwirq].mask) in regmap_del_irq_chip()
1020 virq = irq_find_mapping(d->domain, hwirq); in regmap_del_irq_chip()
1025 irq_domain_remove(d->domain); in regmap_del_irq_chip()
1026 kfree(d->type_buf); in regmap_del_irq_chip()
1027 kfree(d->type_buf_def); in regmap_del_irq_chip()
1028 kfree(d->wake_buf); in regmap_del_irq_chip()
1029 kfree(d->mask_buf_def); in regmap_del_irq_chip()
1030 kfree(d->mask_buf); in regmap_del_irq_chip()
1031 kfree(d->main_status_buf); in regmap_del_irq_chip()
1032 kfree(d->status_reg_buf); in regmap_del_irq_chip()
1033 kfree(d->status_buf); in regmap_del_irq_chip()
1034 kfree(d->prev_status_buf); in regmap_del_irq_chip()
1035 if (d->config_buf) { in regmap_del_irq_chip()
1036 for (i = 0; i < d->chip->num_config_bases; i++) in regmap_del_irq_chip()
1037 kfree(d->config_buf[i]); in regmap_del_irq_chip()
1038 kfree(d->config_buf); in regmap_del_irq_chip()
1040 mutex_destroy(&d->lock); in regmap_del_irq_chip()
1041 lockdep_unregister_key(&d->lock_key); in regmap_del_irq_chip()
1042 kfree(d); in regmap_del_irq_chip()
1048 struct regmap_irq_chip_data *d = *(struct regmap_irq_chip_data **)res; in devm_regmap_irq_chip_release() local
1050 regmap_del_irq_chip(d->irq, d); in devm_regmap_irq_chip_release()
1066 * devm_regmap_add_irq_chip_fwnode() - Resource managed regmap_add_irq_chip_fwnode()
1089 struct regmap_irq_chip_data **ptr, *d; in devm_regmap_add_irq_chip_fwnode() local
1095 return -ENOMEM; in devm_regmap_add_irq_chip_fwnode()
1098 chip, &d); in devm_regmap_add_irq_chip_fwnode()
1104 *ptr = d; in devm_regmap_add_irq_chip_fwnode()
1106 *data = d; in devm_regmap_add_irq_chip_fwnode()
1112 * devm_regmap_add_irq_chip() - Resource managed regmap_add_irq_chip()
1132 return devm_regmap_add_irq_chip_fwnode(dev, dev_fwnode(map->dev), map, in devm_regmap_add_irq_chip()
1139 * devm_regmap_del_irq_chip() - Resource managed regmap_del_irq_chip()
1152 WARN_ON(irq != data->irq); in devm_regmap_del_irq_chip()
1162 * regmap_irq_chip_get_base() - Retrieve interrupt base for a regmap IRQ chip
1170 WARN_ON(!data->irq_base); in regmap_irq_chip_get_base()
1171 return data->irq_base; in regmap_irq_chip_get_base()
1176 * regmap_irq_get_virq() - Map an interrupt on a chip to a virtual IRQ
1186 if (!data->chip->irqs[irq].mask) in regmap_irq_get_virq()
1187 return -EINVAL; in regmap_irq_get_virq()
1189 return irq_create_mapping(data->domain, irq); in regmap_irq_get_virq()
1194 * regmap_irq_get_domain() - Retrieve the irq_domain for the chip
1206 return data->domain; in regmap_irq_get_domain()