Lines Matching full:map
45 static int regcache_count_cacheable_registers(struct regmap *map)
51 for (unsigned int i = 0; i < map->num_reg_defaults_raw; i++)
52 if (regmap_readable(map, i * map->reg_stride) &&
53 !regmap_volatile(map, i * map->reg_stride))
59 static int regcache_hw_init(struct regmap *map)
65 if (!map->reg_defaults_raw) {
66 bool cache_bypass = map->cache_bypass;
67 dev_dbg(map->dev, "No cache defaults, reading back from HW\n");
70 map->cache_bypass = true;
71 tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL);
74 ret = regmap_raw_read(map, 0, tmp_buf,
75 map->cache_size_raw);
76 map->cache_bypass = cache_bypass;
78 map->reg_defaults_raw = tmp_buf;
79 map->cache_free = true;
86 for (unsigned int i = 0, j = 0; i < map->num_reg_defaults_raw; i++) {
87 reg = i * map->reg_stride;
89 if (!regmap_readable(map, reg))
92 if (regmap_volatile(map, reg))
95 if (map->reg_defaults_raw) {
96 val = regcache_get_val(map, map->reg_defaults_raw, i);
98 bool cache_bypass = map->cache_bypass;
100 map->cache_bypass = true;
101 ret = regmap_read(map, reg, &val);
102 map->cache_bypass = cache_bypass;
104 dev_err(map->dev, "Failed to read %x: %d\n",
110 map->reg_defaults[j].reg = reg;
111 map->reg_defaults[j].def = val;
118 static void regcache_hw_exit(struct regmap *map)
120 if (map->cache_free)
121 kfree(map->reg_defaults_raw);
124 int regcache_init(struct regmap *map, const struct regmap_config *config)
131 if (map->cache_type == REGCACHE_NONE) {
133 dev_warn(map->dev,
136 map->cache_bypass = true;
141 dev_err(map->dev,
147 dev_err(map->dev,
153 if (config->reg_defaults[i].reg % map->reg_stride)
157 if (cache_types[i]->type == map->cache_type)
161 dev_err(map->dev, "Could not match cache type: %d\n",
162 map->cache_type);
166 map->num_reg_defaults = config->num_reg_defaults;
167 map->num_reg_defaults_raw = config->num_reg_defaults_raw;
168 map->reg_defaults_raw = config->reg_defaults_raw;
169 map->cache_word_size = BITS_TO_BYTES(config->val_bits);
170 map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw;
172 map->cache = NULL;
173 map->cache_ops = cache_types[i];
175 if (!map->cache_ops->read ||
176 !map->cache_ops->write ||
177 !map->cache_ops->name)
185 tmp_buf = kmemdup_array(config->reg_defaults, map->num_reg_defaults,
186 sizeof(*map->reg_defaults), GFP_KERNEL);
189 map->reg_defaults = tmp_buf;
190 } else if (map->num_reg_defaults_raw) {
191 count = regcache_count_cacheable_registers(map);
193 map->cache_bypass = true;
196 if (map->cache_bypass)
199 map->num_reg_defaults = count;
200 map->reg_defaults = kmalloc_objs(struct reg_default, count);
201 if (!map->reg_defaults)
205 if (!map->max_register_is_set && map->num_reg_defaults_raw) {
206 map->max_register = (map->num_reg_defaults_raw - 1) * map->reg_stride;
207 map->max_register_is_set = true;
210 if (map->cache_ops->init) {
211 dev_dbg(map->dev, "Initializing %s cache\n",
212 map->cache_ops->name);
213 map->lock(map->lock_arg);
214 ret = map->cache_ops->init(map);
215 map->unlock(map->lock_arg);
226 ret = regcache_hw_init(map);
231 if (map->cache_ops->populate &&
232 (map->num_reg_defaults || map->reg_default_cb)) {
233 dev_dbg(map->dev, "Populating %s cache\n", map->cache_ops->name);
234 map->lock(map->lock_arg);
235 ret = map->cache_ops->populate(map);
236 map->unlock(map->lock_arg);
243 regcache_hw_exit(map);
245 if (map->cache_ops->exit) {
246 dev_dbg(map->dev, "Destroying %s cache\n", map->cache_ops->name);
247 map->lock(map->lock_arg);
248 ret = map->cache_ops->exit(map);
249 map->unlock(map->lock_arg);
252 kfree(map->reg_defaults);
257 void regcache_exit(struct regmap *map)
259 if (map->cache_type == REGCACHE_NONE)
262 BUG_ON(!map->cache_ops);
264 regcache_hw_exit(map);
266 if (map->cache_ops->exit) {
267 dev_dbg(map->dev, "Destroying %s cache\n",
268 map->cache_ops->name);
269 map->lock(map->lock_arg);
270 map->cache_ops->exit(map);
271 map->unlock(map->lock_arg);
274 kfree(map->reg_defaults);
280 * @map: map to configure.
286 int regcache_read(struct regmap *map,
291 if (map->cache_type == REGCACHE_NONE)
294 BUG_ON(!map->cache_ops);
296 if (!regmap_volatile(map, reg)) {
297 ret = map->cache_ops->read(map, reg, value);
300 trace_regmap_reg_read_cache(map, reg, *value);
311 * @map: map to configure.
317 int regcache_write(struct regmap *map,
320 if (map->cache_type == REGCACHE_NONE)
323 BUG_ON(!map->cache_ops);
325 if (!regmap_volatile(map, reg))
326 return map->cache_ops->write(map, reg, value);
331 bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg,
336 if (!regmap_writeable(map, reg))
340 if (!map->no_sync_defaults)
344 ret = regcache_lookup_reg(map, reg);
345 if (ret >= 0 && val == map->reg_defaults[ret].def)
350 static int regcache_default_sync(struct regmap *map, unsigned int min,
355 for (reg = min; reg <= max; reg += map->reg_stride) {
359 if (regmap_volatile(map, reg) ||
360 !regmap_writeable(map, reg))
363 ret = regcache_read(map, reg, &val);
369 if (!regcache_reg_needs_sync(map, reg, val))
372 map->cache_bypass = true;
373 ret = _regmap_write(map, reg, val);
374 map->cache_bypass = false;
376 dev_err(map->dev, "Unable to sync register %#x. %d\n",
380 dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val);
394 * @map: map to configure.
402 int regcache_sync(struct regmap *map)
410 if (WARN_ON(map->cache_type == REGCACHE_NONE))
413 BUG_ON(!map->cache_ops);
415 map->lock(map->lock_arg);
417 bypass = map->cache_bypass;
418 dev_dbg(map->dev, "Syncing %s cache\n",
419 map->cache_ops->name);
420 name = map->cache_ops->name;
421 trace_regcache_sync(map, name, "start");
423 if (!map->cache_dirty)
427 map->cache_bypass = true;
428 for (i = 0; i < map->patch_regs; i++) {
429 ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def);
431 dev_err(map->dev, "Failed to write %x = %x: %d\n",
432 map->patch[i].reg, map->patch[i].def, ret);
436 map->cache_bypass = false;
438 if (map->cache_ops->sync)
439 ret = map->cache_ops->sync(map, 0, map->max_register);
441 ret = regcache_default_sync(map, 0, map->max_register);
444 map->cache_dirty = false;
448 map->cache_bypass = bypass;
449 map->no_sync_defaults = false;
457 rb_for_each(node, NULL, &map->range_tree, rbtree_all) {
462 if (regcache_read(map, this->selector_reg, &i) != 0)
465 ret = _regmap_write(map, this->selector_reg, i);
467 dev_err(map->dev, "Failed to write %x = %x: %d\n",
473 map->unlock(map->lock_arg);
475 regmap_async_complete(map);
477 trace_regcache_sync(map, name, "stop");
486 * @map: map to sync.
495 int regcache_sync_region(struct regmap *map, unsigned int min,
502 if (WARN_ON(map->cache_type == REGCACHE_NONE))
505 BUG_ON(!map->cache_ops);
507 map->lock(map->lock_arg);
510 bypass = map->cache_bypass;
512 name = map->cache_ops->name;
513 dev_dbg(map->dev, "Syncing %s cache from %#x-%#x\n", name, min, max);
515 trace_regcache_sync(map, name, "start region");
517 if (!map->cache_dirty)
520 map->async = true;
522 if (map->cache_ops->sync)
523 ret = map->cache_ops->sync(map, min, max);
525 ret = regcache_default_sync(map, min, max);
529 map->cache_bypass = bypass;
530 map->async = false;
531 map->no_sync_defaults = false;
532 map->unlock(map->lock_arg);
534 regmap_async_complete(map);
536 trace_regcache_sync(map, name, "stop region");
545 * @map: map to operate on
553 int regcache_drop_region(struct regmap *map, unsigned int min,
558 if (!map->cache_ops || !map->cache_ops->drop)
561 map->lock(map->lock_arg);
563 trace_regcache_drop_region(map, min, max);
565 ret = map->cache_ops->drop(map, min, max);
567 map->unlock(map->lock_arg);
574 * regcache_cache_only - Put a register map into cache only mode
576 * @map: map to configure
579 * When a register map is marked as cache only writes to the register
580 * map API will only update the register cache, they will not cause
585 void regcache_cache_only(struct regmap *map, bool enable)
587 map->lock(map->lock_arg);
588 WARN_ON(map->cache_type != REGCACHE_NONE &&
589 map->cache_bypass && enable);
590 map->cache_only = enable;
591 trace_regmap_cache_only(map, enable);
592 map->unlock(map->lock_arg);
599 * @map: map to mark
609 void regcache_mark_dirty(struct regmap *map)
611 map->lock(map->lock_arg);
612 map->cache_dirty = true;
613 map->no_sync_defaults = true;
614 map->unlock(map->lock_arg);
619 * regcache_cache_bypass - Put a register map into cache bypass mode
621 * @map: map to configure
624 * When a register map is marked with the cache bypass option, writes
625 * to the register map API will only update the hardware and not
629 void regcache_cache_bypass(struct regmap *map, bool enable)
631 map->lock(map->lock_arg);
632 WARN_ON(map->cache_only && enable);
633 map->cache_bypass = enable;
634 trace_regmap_cache_bypass(map, enable);
635 map->unlock(map->lock_arg);
642 * @map: map to check
647 bool regcache_reg_cached(struct regmap *map, unsigned int reg)
652 map->lock(map->lock_arg);
654 ret = regcache_read(map, reg, &val);
656 map->unlock(map->lock_arg);
662 void regcache_set_val(struct regmap *map, void *base, unsigned int idx,
666 if (map->format.format_val) {
667 map->format.format_val(base + (map->cache_word_size * idx),
672 switch (map->cache_word_size) {
696 unsigned int regcache_get_val(struct regmap *map, const void *base,
703 if (map->format.parse_val)
704 return map->format.parse_val(regcache_get_val_addr(map, base,
707 switch (map->cache_word_size) {
738 int regcache_lookup_reg(struct regmap *map, unsigned int reg)
746 r = bsearch(&key, map->reg_defaults, map->num_reg_defaults,
750 return r - map->reg_defaults;
763 int regcache_sync_val(struct regmap *map, unsigned int reg, unsigned int val)
767 if (!regcache_reg_needs_sync(map, reg, val))
770 map->cache_bypass = true;
772 ret = _regmap_write(map, reg, val);
774 map->cache_bypass = false;
777 dev_err(map->dev, "Unable to sync register %#x. %d\n",
781 dev_dbg(map->dev, "Synced register %#x, value %#x\n",
787 static int regcache_sync_block_single(struct regmap *map, void *block,
796 regtmp = block_base + (i * map->reg_stride);
799 !regmap_writeable(map, regtmp))
802 val = regcache_get_val(map, block, i);
803 ret = regcache_sync_val(map, regtmp, val);
811 static int regcache_sync_block_raw_flush(struct regmap *map, const void **data,
814 size_t val_bytes = map->format.val_bytes;
820 count = (cur - base) / map->reg_stride;
822 dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n",
823 count * val_bytes, count, base, cur - map->reg_stride);
825 map->cache_bypass = true;
827 ret = _regmap_raw_write(map, base, *data, count * val_bytes, false);
829 dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n",
830 base, cur - map->reg_stride, ret);
832 map->cache_bypass = false;
839 static int regcache_sync_block_raw(struct regmap *map, void *block,
851 regtmp = block_base + (i * map->reg_stride);
854 !regmap_writeable(map, regtmp)) {
855 ret = regcache_sync_block_raw_flush(map, &data,
862 val = regcache_get_val(map, block, i);
863 if (!regcache_reg_needs_sync(map, regtmp, val)) {
864 ret = regcache_sync_block_raw_flush(map, &data,
872 data = regcache_get_val_addr(map, block, i);
877 return regcache_sync_block_raw_flush(map, &data, base, regtmp +
878 map->reg_stride);
881 int regcache_sync_block(struct regmap *map, void *block,
886 if (regmap_can_raw_write(map) && !map->use_single_write)
887 return regcache_sync_block_raw(map, block, cache_present,
890 return regcache_sync_block_single(map, block, cache_present,