Lines Matching +full:0 +full:x6800
49 #define IF_IADBG_INIT_ADAPTER 0x00000001 // init adapter info
50 #define IF_IADBG_TX 0x00000002 // debug TX
51 #define IF_IADBG_RX 0x00000004 // debug RX
52 #define IF_IADBG_QUERY_INFO 0x00000008 // debug Request call
53 #define IF_IADBG_SHUTDOWN 0x00000010 // debug shutdown event
54 #define IF_IADBG_INTR 0x00000020 // debug interrupt DPC
55 #define IF_IADBG_TXPKT 0x00000040 // debug TX PKT
56 #define IF_IADBG_RXPKT 0x00000080 // debug RX PKT
57 #define IF_IADBG_ERR 0x00000100 // debug system error
58 #define IF_IADBG_EVENT 0x00000200 // debug event
59 #define IF_IADBG_DIS_INTR 0x00001000 // debug disable interrupt
60 #define IF_IADBG_EN_INTR 0x00002000 // debug enable interrupt
61 #define IF_IADBG_LOUD 0x00004000 // debugging info
62 #define IF_IADBG_VERY_LOUD 0x00008000 // excessive debugging info
63 #define IF_IADBG_CBR 0x00100000 //
64 #define IF_IADBG_UBR 0x00200000 //
65 #define IF_IADBG_ABR 0x00400000 //
66 #define IF_IADBG_DESC 0x01000000 //
67 #define IF_IADBG_SUNI_STAT 0x02000000 // suni statistics
68 #define IF_IADBG_RESET 0x04000000
133 #define IA_CMD 0x7749
144 #define MEMDUMP 0x01
147 #define MEMDUMP_SEGREG 0x2
148 #define MEMDUMP_DEV 0x1
149 #define MEMDUMP_REASSREG 0x3
150 #define MEMDUMP_FFL 0x4
151 #define READ_REG 0x5
152 #define WAKE_DBG_WAIT 0x6
156 #define Boolean(x) ((x) ? 1 : 0)
161 #define MEM_VALID 0xfffffff0 /* mask base address with this */
164 #define PCI_VENDOR_ID_IPHASE 0x107e
167 #define PCI_DEVICE_ID_IPHASE_5575 0x0008
172 #define MCR 0
177 #define NRMCODE 5 /* 0 - 7 */
178 #define TRMCODE 3 /* 0 - 7 */
180 #define ATDFCODE 2 /* 0 - 15 */
183 #define TX_PACKET_RAM 0x00000 /* start of Trasnmit Packet memory - 0 */
186 - descriptor 0 unused */
187 #define REASS_RAM_SIZE 0x10000 /* for 64K 1K VC board */
188 #define RX_PACKET_RAM 0x80000 /* start of Receive Packet memory - 512K */
191 - descriptor 0 unused */
236 #define ABR 0x8000
237 #define UBR 0xc000
238 #define CBR 0x0000
257 #define UIOLI 0x80
258 #define CRC_APPEND 0x40 /* for status field - CRC-32 append */
259 #define ABR_STATE 0x02
275 #define DMA_INT_ENABLE 0x0002 /* use for both Tx and Rx */
276 #define TX_DLE_PSI 0x0001
331 #define EPROM_SIZE 0x40000 /* says 64K in the docs ??? */
336 #define IPHASE5575_PCI_CONFIG_REG_BASE 0x0000
337 #define IPHASE5575_BUS_CONTROL_REG_BASE 0x1000 /* offsets 0x00 - 0x3c */
338 #define IPHASE5575_FRAG_CONTROL_REG_BASE 0x2000
339 #define IPHASE5575_REASS_CONTROL_REG_BASE 0x3000
340 #define IPHASE5575_DMA_CONTROL_REG_BASE 0x4000
342 #define IPHASE5575_FRAG_CONTROL_RAM_BASE 0x10000
343 #define IPHASE5575_REASS_CONTROL_RAM_BASE 0x20000
346 #define IPHASE5575_BUS_CONTROL_REG 0x00
347 #define IPHASE5575_BUS_STATUS_REG 0x01 /* actual offset 0x04 */
348 #define IPHASE5575_MAC1 0x02
349 #define IPHASE5575_REV 0x03
350 #define IPHASE5575_MAC2 0x03 /*actual offset 0x0e-reg 0x0c*/
351 #define IPHASE5575_EXT_RESET 0x04
352 #define IPHASE5575_INT_RESET 0x05 /* addr 1c ?? reg 0x06 */
353 #define IPHASE5575_PCI_ADDR_PAGE 0x07 /* reg 0x08, 0x09 ?? */
354 #define IPHASE5575_EEPROM_ACCESS 0x0a /* actual offset 0x28 */
355 #define IPHASE5575_CELL_FIFO_QUEUE_SZ 0x0b
356 #define IPHASE5575_CELL_FIFO_MARK_STATE 0x0c
357 #define IPHASE5575_CELL_FIFO_READ_PTR 0x0d
358 #define IPHASE5575_CELL_FIFO_WRITE_PTR 0x0e
359 #define IPHASE5575_CELL_FIFO_CELLS_AVL 0x0f /* actual offset 0x3c */
362 #define CTRL_FE_RST 0x80000000
363 #define CTRL_LED 0x40000000
364 #define CTRL_25MBPHY 0x10000000
365 #define CTRL_ENCMBMEM 0x08000000
366 #define CTRL_ENOFFSEG 0x01000000
367 #define CTRL_ERRMASK 0x00400000
368 #define CTRL_DLETMASK 0x00100000
369 #define CTRL_DLERMASK 0x00080000
370 #define CTRL_FEMASK 0x00040000
371 #define CTRL_SEGMASK 0x00020000
372 #define CTRL_REASSMASK 0x00010000
373 #define CTRL_CSPREEMPT 0x00002000
374 #define CTRL_B128 0x00000200
375 #define CTRL_B64 0x00000100
376 #define CTRL_B48 0x00000080
377 #define CTRL_B32 0x00000040
378 #define CTRL_B16 0x00000020
379 #define CTRL_B8 0x00000010
382 #define STAT_CMEMSIZ 0xc0000000
383 #define STAT_ADPARCK 0x20000000
384 #define STAT_RESVD 0x1fffff80
385 #define STAT_ERRINT 0x00000040
386 #define STAT_MARKINT 0x00000020
387 #define STAT_DLETINT 0x00000010
388 #define STAT_DLERINT 0x00000008
389 #define STAT_FEINT 0x00000004
390 #define STAT_SEGINT 0x00000002
391 #define STAT_REASSINT 0x00000001
397 #define IDLEHEADHI 0x00
398 #define IDLEHEADLO 0x01
399 #define MAXRATE 0x02
401 #define RATE155 0x64b1 // 16 bits float format
403 #define RATE25 0x5f9d
405 #define STPARMS 0x03
406 #define STPARMS_1K 0x008c
407 #define STPARMS_2K 0x0049
408 #define STPARMS_4K 0x0026
409 #define COMP_EN 0x4000
410 #define CBR_EN 0x2000
411 #define ABR_EN 0x0800
412 #define UBR_EN 0x0400
414 #define ABRUBR_ARB 0x04
415 #define RM_TYPE 0x05
416 /*Value for RM_TYPE register for ATM Forum Traffic Mangement4.0 support*/
417 #define RM_TYPE_4_0 0x0100
419 #define SEG_COMMAND_REG 0x17
421 #define RESET_SEG 0x0055
422 #define RESET_SEG_STATE 0x00aa
423 #define RESET_TX_CELL_CTR 0x00cc
425 #define CBR_PTR_BASE 0x20
426 #define ABR_SBPTR_BASE 0x22
427 #define UBR_SBPTR_BASE 0x23
428 #define ABRWQ_BASE 0x26
429 #define UBRWQ_BASE 0x27
430 #define VCT_BASE 0x28
431 #define VCTE_BASE 0x29
432 #define CBR_TAB_BEG 0x2c
433 #define CBR_TAB_END 0x2d
434 #define PRQ_ST_ADR 0x30
435 #define PRQ_ED_ADR 0x31
436 #define PRQ_RD_PTR 0x32
437 #define PRQ_WR_PTR 0x33
438 #define TCQ_ST_ADR 0x34
439 #define TCQ_ED_ADR 0x35
440 #define TCQ_RD_PTR 0x36
441 #define TCQ_WR_PTR 0x37
442 #define SEG_QUEUE_BASE 0x40
443 #define SEG_DESC_BASE 0x41
444 #define MODE_REG_0 0x45
445 #define T_ONLINE 0x0002 /* (i)chipSAR is online */
447 #define MODE_REG_1 0x46
448 #define MODE_REG_1_VAL 0x0400 /*for propoer device operation*/
450 #define SEG_INTR_STATUS_REG 0x47
451 #define SEG_MASK_REG 0x48
452 #define TRANSMIT_DONE 0x0200
453 #define TCQ_NOT_EMPTY 0x1000 /* this can be used for both the interrupt
456 #define CELL_CTR_HIGH_AUTO 0x49
457 #define CELL_CTR_HIGH_NOAUTO 0xc9
458 #define CELL_CTR_LO_AUTO 0x4a
459 #define CELL_CTR_LO_NOAUTO 0xca
462 #define NEXTDESC 0x59
463 #define NEXTVC 0x5a
464 #define PSLOTCNT 0x5d
465 #define NEWDN 0x6a
466 #define NEWVC 0x6b
467 #define SBPTR 0x6c
468 #define ABRWQ_WRPTR 0x6f
469 #define ABRWQ_RDPTR 0x70
470 #define UBRWQ_WRPTR 0x71
471 #define UBRWQ_RDPTR 0x72
472 #define CBR_VC 0x73
473 #define ABR_SBVC 0x75
474 #define UBR_SBVC 0x76
475 #define ABRNEXTLINK 0x78
476 #define UBRNEXTLINK 0x79
482 #define MODE_REG 0x00
483 #define R_ONLINE 0x0002 /* (i)chip is online */
484 #define IGN_RAW_FL 0x0004
486 #define PROTOCOL_ID 0x01
487 #define REASS_MASK_REG 0x02
488 #define REASS_INTR_STATUS_REG 0x03
490 #define RX_PKT_CTR_OF 0x8000
491 #define RX_ERR_CTR_OF 0x4000
492 #define RX_CELL_CTR_OF 0x1000
493 #define RX_FREEQ_EMPT 0x0200
494 #define RX_EXCPQ_FL 0x0080
495 #define RX_RAWQ_FL 0x0010
496 #define RX_EXCP_RCVD 0x0008
497 #define RX_PKT_RCVD 0x0004
498 #define RX_RAW_RCVD 0x0001
500 #define DRP_PKT_CNTR 0x04
501 #define ERR_CNTR 0x05
502 #define RAW_BASE_ADR 0x08
503 #define CELL_CTR0 0x0c
504 #define CELL_CTR1 0x0d
505 #define REASS_COMMAND_REG 0x0f
507 #define RESET_REASS 0x0055
508 #define RESET_REASS_STATE 0x00aa
509 #define RESET_DRP_PKT_CNTR 0x00f1
510 #define RESET_ERR_CNTR 0x00f2
511 #define RESET_CELL_CNTR 0x00f8
512 #define RESET_REASS_ALL_REGS 0x00ff
514 #define REASS_DESC_BASE 0x10
515 #define VC_LKUP_BASE 0x11
516 #define REASS_TABLE_BASE 0x12
517 #define REASS_QUEUE_BASE 0x13
518 #define PKT_TM_CNT 0x16
519 #define TMOUT_RANGE 0x17
520 #define INTRVL_CNTR 0x18
521 #define TMOUT_INDX 0x19
522 #define VP_LKUP_BASE 0x1c
523 #define VP_FILTER 0x1d
524 #define ABR_LKUP_BASE 0x1e
525 #define FREEQ_ST_ADR 0x24
526 #define FREEQ_ED_ADR 0x25
527 #define FREEQ_RD_PTR 0x26
528 #define FREEQ_WR_PTR 0x27
529 #define PCQ_ST_ADR 0x28
530 #define PCQ_ED_ADR 0x29
531 #define PCQ_RD_PTR 0x2a
532 #define PCQ_WR_PTR 0x2b
533 #define EXCP_Q_ST_ADR 0x2c
534 #define EXCP_Q_ED_ADR 0x2d
535 #define EXCP_Q_RD_PTR 0x2e
536 #define EXCP_Q_WR_PTR 0x2f
537 #define CC_FIFO_ST_ADR 0x34
538 #define CC_FIFO_ED_ADR 0x35
539 #define CC_FIFO_RD_PTR 0x36
540 #define CC_FIFO_WR_PTR 0x37
541 #define STATE_REG 0x38
542 #define BUF_SIZE 0x42
543 #define XTRA_RM_OFFSET 0x44
544 #define DRP_PKT_CNTR_NC 0x84
545 #define ERR_CNTR_NC 0x85
546 #define CELL_CNTR0_NC 0x8c
547 #define CELL_CNTR1_NC 0x8d
550 #define EXCPQ_EMPTY 0x0040
551 #define PCQ_EMPTY 0x0010
552 #define FREEQ_EMPTY 0x0004
562 #define IPHASE5575_TX_COUNTER 0x200 /* offset - 0x800 */
563 #define IPHASE5575_RX_COUNTER 0x280 /* offset - 0xa00 */
564 #define IPHASE5575_TX_LIST_ADDR 0x300 /* offset - 0xc00 */
565 #define IPHASE5575_RX_LIST_ADDR 0x380 /* offset - 0xe00 */
571 #define TX_DESC_BASE 0x0000 /* Buffer Decriptor Table */
572 #define TX_COMP_Q 0x1000 /* Transmit Complete Queue */
573 #define PKT_RDY_Q 0x1400 /* Packet Ready Queue */
574 #define CBR_SCHED_TABLE 0x1800 /* CBR Table */
575 #define UBR_SCHED_TABLE 0x3000 /* UBR Table */
576 #define UBR_WAIT_Q 0x4000 /* UBR Wait Queue */
577 #define ABR_SCHED_TABLE 0x5000 /* ABR Table */
578 #define ABR_WAIT_Q 0x5800 /* ABR Wait Queue */
579 #define EXT_VC_TABLE 0x6000 /* Extended VC Table */
580 #define MAIN_VC_TABLE 0x8000 /* Main VC Table */
586 #define DESC_MODE 0x0
587 #define VC_INDEX 0x1
588 #define BYTE_CNT 0x3
589 #define PKT_START_HI 0x4
590 #define PKT_START_LO 0x5
593 #define EOM_EN 0x0800
594 #define AAL5 0x0100
595 #define APP_CRC32 0x0400
596 #define CMPL_INT 0x1000
599 (((unsigned long)(db & 0x04)) << 16) | (dn << 5) | (to << 1)
602 #define RX_DESC_BASE 0x0000 /* Buffer Descriptor Table */
603 #define VP_TABLE 0x5c00 /* VP Table */
604 #define EXCEPTION_Q 0x5e00 /* Exception Queue */
605 #define FREE_BUF_DESC_Q 0x6000 /* Free Buffer Descriptor Queue */
606 #define PKT_COMP_Q 0x6800 /* Packet Complete Queue */
607 #define REASS_TABLE 0x7000 /* Reassembly Table */
608 #define RX_VC_TABLE 0x7800 /* VC Table */
609 #define ABR_VC_TABLE 0x8000 /* ABR VC Table */
616 #define RX_ACT 0x8000
617 #define RX_VPVC 0x4000
618 #define RX_CNG 0x0040
619 #define RX_CER 0x0008
620 #define RX_PTE 0x0004
621 #define RX_OFL 0x0002
625 #define NO_AAL5_PKT 0x0000
626 #define AAL5_PKT_REASSEMBLED 0x4000
627 #define AAL5_PKT_TERMINATED 0x8000
628 #define RAW_PKT 0xc000
629 #define REASS_ABR 0x2000
646 ffreg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */
648 u_int filler5[0x17 - 0x06];
650 u_int filler18[0x20 - 0x18];
661 u_int filler2a[0x2C - 0x2A];
665 u_int filler2f[0x30 - 0x2F];
674 u_int filler38[0x40 - 0x38];
677 u_int filler42[0x45 - 0x42];
678 ffreg_t mode_reg_0; /* Mode register 0 */
685 u_int filler4c[0x58 - 0x4c];
689 u_int filler5b[0x5d - 0x5b];
691 u_int filler5e[0x6a - 0x5e];
708 u_int filler7a[0x7c-0x7a];
710 u_int filler7d[0xca-0x7d]; /* pad out to full address space */
713 u_int fillercc[0x100-0xcc]; /* pad out to full address space */
717 rreg_t mode_reg_0; /* Mode register 0 */
723 u_int filler6[0x08 - 0x06];
725 u_int filler2[0x0c - 0x09];
726 rreg_t cell_ctr0; /* Cell Counter 0 (cleared when read) */
728 u_int filler3[0x0f - 0x0e];
734 u_int filler14[0x16 - 0x14];
739 u_int filler1a[0x1c - 0x1a];
743 u_int filler1f[0x24 - 0x1f];
756 u_int filler30[0x34 - 0x30];
762 u_int filler39[0x42 - 0x39];
766 u_int filler45[0x84 - 0x45];
769 u_int filler86[0x8c - 0x86];
770 rreg_t cell_ctr0_nc; /* Cell Counter 0, Not clear on read */
772 u_int filler8e[0x100-0x8e]; /* pad out to full address space */
821 #if 0 /* Additional Parameters of TM 4.0 */
826 #endif /* 0 */
854 #define VC_ACTIVE 0x01
855 #define VC_ABR 0x02
856 #define VC_UBR 0x04
890 #define SUNI_LOSV 0x04
892 SUNI_MASTER_RESET = 0x000, /* SUNI Master Reset and Identity */
893 SUNI_MASTER_CONFIG = 0x004, /* SUNI Master Configuration */
894 SUNI_MASTER_INTR_STAT = 0x008, /* SUNI Master Interrupt Status */
895 SUNI_RESERVED1 = 0x00c, /* Reserved */
896 SUNI_MASTER_CLK_MONITOR = 0x010, /* SUNI Master Clock Monitor */
897 SUNI_MASTER_CONTROL = 0x014, /* SUNI Master Clock Monitor */
899 SUNI_RSOP_CONTROL = 0x040, /* RSOP Control/Interrupt Enable */
900 SUNI_RSOP_STATUS = 0x044, /* RSOP Status/Interrupt States */
901 SUNI_RSOP_SECTION_BIP8L = 0x048, /* RSOP Section BIP-8 LSB */
902 SUNI_RSOP_SECTION_BIP8M = 0x04c, /* RSOP Section BIP-8 MSB */
904 SUNI_TSOP_CONTROL = 0x050, /* TSOP Control */
905 SUNI_TSOP_DIAG = 0x054, /* TSOP Disgnostics */
907 SUNI_RLOP_CS = 0x060, /* RLOP Control/Status */
908 SUNI_RLOP_INTR = 0x064, /* RLOP Interrupt Enable/Status */
909 SUNI_RLOP_LINE_BIP24L = 0x068, /* RLOP Line BIP-24 LSB */
910 SUNI_RLOP_LINE_BIP24 = 0x06c, /* RLOP Line BIP-24 */
911 SUNI_RLOP_LINE_BIP24M = 0x070, /* RLOP Line BIP-24 MSB */
912 SUNI_RLOP_LINE_FEBEL = 0x074, /* RLOP Line FEBE LSB */
913 SUNI_RLOP_LINE_FEBE = 0x078, /* RLOP Line FEBE */
914 SUNI_RLOP_LINE_FEBEM = 0x07c, /* RLOP Line FEBE MSB */
916 SUNI_TLOP_CONTROL = 0x080, /* TLOP Control */
917 SUNI_TLOP_DISG = 0x084, /* TLOP Disgnostics */
919 SUNI_RPOP_CS = 0x0c0, /* RPOP Status/Control */
920 SUNI_RPOP_INTR = 0x0c4, /* RPOP Interrupt/Status */
921 SUNI_RPOP_RESERVED = 0x0c8, /* RPOP Reserved */
922 SUNI_RPOP_INTR_ENA = 0x0cc, /* RPOP Interrupt Enable */
924 SUNI_RPOP_PATH_SIG = 0x0dc, /* RPOP Path Signal Label */
925 SUNI_RPOP_BIP8L = 0x0e0, /* RPOP Path BIP-8 LSB */
926 SUNI_RPOP_BIP8M = 0x0e4, /* RPOP Path BIP-8 MSB */
927 SUNI_RPOP_FEBEL = 0x0e8, /* RPOP Path FEBE LSB */
928 SUNI_RPOP_FEBEM = 0x0ec, /* RPOP Path FEBE MSB */
930 SUNI_TPOP_CNTRL_DAIG = 0x100, /* TPOP Control/Disgnostics */
931 SUNI_TPOP_POINTER_CTRL = 0x104, /* TPOP Pointer Control */
932 SUNI_TPOP_SOURCER_CTRL = 0x108, /* TPOP Source Control */
934 SUNI_TPOP_ARB_PRTL = 0x114, /* TPOP Arbitrary Pointer LSB */
935 SUNI_TPOP_ARB_PRTM = 0x118, /* TPOP Arbitrary Pointer MSB */
936 SUNI_TPOP_RESERVED2 = 0x11c, /* TPOP Reserved */
937 SUNI_TPOP_PATH_SIG = 0x120, /* TPOP Path Signal Lable */
938 SUNI_TPOP_PATH_STATUS = 0x124, /* TPOP Path Status */
940 SUNI_RACP_CS = 0x140, /* RACP Control/Status */
941 SUNI_RACP_INTR = 0x144, /* RACP Interrupt Enable/Status */
942 SUNI_RACP_HDR_PATTERN = 0x148, /* RACP Match Header Pattern */
943 SUNI_RACP_HDR_MASK = 0x14c, /* RACP Match Header Mask */
944 SUNI_RACP_CORR_HCS = 0x150, /* RACP Correctable HCS Error Count */
945 SUNI_RACP_UNCORR_HCS = 0x154, /* RACP Uncorrectable HCS Err Count */
947 SUNI_TACP_CONTROL = 0x180, /* TACP Control */
948 SUNI_TACP_IDLE_HDR_PAT = 0x184, /* TACP Idle Cell Header Pattern */
949 SUNI_TACP_IDLE_PAY_PAY = 0x188, /* TACP Idle Cell Payld Octet Patrn */
953 * SUNI_MASTER_TEST = 0x200, SUNI Master Test */
954 SUNI_RESERVED_TEST = 0x204 /* SUNI Reserved for Test */
1064 MB25_MASTER_CTRL = 0x00, /* Master control */
1065 MB25_INTR_STATUS = 0x04, /* Interrupt status */
1066 MB25_DIAG_CONTROL = 0x08, /* Diagnostic control */
1067 MB25_LED_HEC = 0x0c, /* LED driver and HEC status/control */
1068 MB25_LOW_BYTE_COUNTER = 0x10,
1069 MB25_HIGH_BYTE_COUNTER = 0x14
1075 #define MB25_MC_UPLO 0x80 /* UPLO */
1076 #define MB25_MC_DREC 0x40 /* Discard receive cell errors */
1077 #define MB25_MC_ECEIO 0x20 /* Enable Cell Error Interrupts Only */
1078 #define MB25_MC_TDPC 0x10 /* Transmit data parity check */
1079 #define MB25_MC_DRIC 0x08 /* Discard receive idle cells */
1080 #define MB25_MC_HALTTX 0x04 /* Halt Tx */
1081 #define MB25_MC_UMS 0x02 /* UTOPIA mode select */
1082 #define MB25_MC_ENABLED 0x01 /* Enable interrupt */
1087 #define MB25_IS_GSB 0x40 /* GOOD Symbol Bit */
1088 #define MB25_IS_HECECR 0x20 /* HEC error cell received */
1089 #define MB25_IS_SCR 0x10 /* "Short Cell" Received */
1090 #define MB25_IS_TPE 0x08 /* Trnamsit Parity Error */
1091 #define MB25_IS_RSCC 0x04 /* Receive Signal Condition change */
1092 #define MB25_IS_RCSE 0x02 /* Received Cell Symbol Error */
1093 #define MB25_IS_RFIFOO 0x01 /* Received FIFO Overrun */
1098 #define MB25_DC_FTXCD 0x80 /* Force TxClav deassert */
1099 #define MB25_DC_RXCOS 0x40 /* RxClav operation select */
1100 #define MB25_DC_ECEIO 0x20 /* Single/Multi-PHY config select */
1101 #define MB25_DC_RLFLUSH 0x10 /* Clear receive FIFO */
1102 #define MB25_DC_IXPE 0x08 /* Insert xmit payload error */
1103 #define MB25_DC_IXHECE 0x04 /* Insert Xmit HEC Error */
1104 #define MB25_DC_LB_MASK 0x03 /* Loopback control mask */
1106 #define MB25_DC_LL 0x03 /* Line Loopback */
1107 #define MB25_DC_PL 0x02 /* PHY Loopback */
1108 #define MB25_DC_NM 0x00
1110 #define FE_MASK 0x00F0
1111 #define FE_MULTI_MODE 0x0000
1112 #define FE_SINGLE_MODE 0x0010
1113 #define FE_UTP_OPTION 0x0020
1114 #define FE_25MBIT_PHY 0x0040
1115 #define FE_DS3_PHY 0x0080 /* DS3 */
1116 #define FE_E3_PHY 0x0090 /* E3 */
1120 SUNI_CONFIG = 0x000, /* SUNI Configuration */
1121 SUNI_INTR_ENBL = 0x004, /* SUNI Interrupt Enable */
1122 SUNI_INTR_STAT = 0x008, /* SUNI Interrupt Status */
1123 SUNI_CONTROL = 0x00c, /* SUNI Control */
1124 SUNI_ID_RESET = 0x010, /* SUNI Reset and Identity */
1125 SUNI_DATA_LINK_CTRL = 0x014,
1126 SUNI_RBOC_CONF_INTR_ENBL = 0x018,
1127 SUNI_RBOC_STAT = 0x01c,
1128 SUNI_DS3_FRM_CFG = 0x020,
1129 SUNI_DS3_FRM_INTR_ENBL = 0x024,
1130 SUNI_DS3_FRM_INTR_STAT = 0x028,
1131 SUNI_DS3_FRM_STAT = 0x02c,
1132 SUNI_RFDL_CFG = 0x030,
1133 SUNI_RFDL_ENBL_STAT = 0x034,
1134 SUNI_RFDL_STAT = 0x038,
1135 SUNI_RFDL_DATA = 0x03c,
1136 SUNI_PMON_CHNG = 0x040,
1137 SUNI_PMON_INTR_ENBL_STAT = 0x044,
1138 /* SUNI_RESERVED1 (0x13 - 0x11) */
1139 SUNI_PMON_LCV_EVT_CNT_LSB = 0x050,
1140 SUNI_PMON_LCV_EVT_CNT_MSB = 0x054,
1141 SUNI_PMON_FBE_EVT_CNT_LSB = 0x058,
1142 SUNI_PMON_FBE_EVT_CNT_MSB = 0x05c,
1143 SUNI_PMON_SEZ_DET_CNT_LSB = 0x060,
1144 SUNI_PMON_SEZ_DET_CNT_MSB = 0x064,
1145 SUNI_PMON_PE_EVT_CNT_LSB = 0x068,
1146 SUNI_PMON_PE_EVT_CNT_MSB = 0x06c,
1147 SUNI_PMON_PPE_EVT_CNT_LSB = 0x070,
1148 SUNI_PMON_PPE_EVT_CNT_MSB = 0x074,
1149 SUNI_PMON_FEBE_EVT_CNT_LSB = 0x078,
1150 SUNI_PMON_FEBE_EVT_CNT_MSB = 0x07c,
1151 SUNI_DS3_TRAN_CFG = 0x080,
1152 SUNI_DS3_TRAN_DIAG = 0x084,
1153 /* SUNI_RESERVED2 (0x23 - 0x21) */
1154 SUNI_XFDL_CFG = 0x090,
1155 SUNI_XFDL_INTR_ST = 0x094,
1156 SUNI_XFDL_XMIT_DATA = 0x098,
1157 SUNI_XBOC_CODE = 0x09c,
1158 SUNI_SPLR_CFG = 0x0a0,
1159 SUNI_SPLR_INTR_EN = 0x0a4,
1160 SUNI_SPLR_INTR_ST = 0x0a8,
1161 SUNI_SPLR_STATUS = 0x0ac,
1162 SUNI_SPLT_CFG = 0x0b0,
1163 SUNI_SPLT_CNTL = 0x0b4,
1164 SUNI_SPLT_DIAG_G1 = 0x0b8,
1165 SUNI_SPLT_F1 = 0x0bc,
1166 SUNI_CPPM_LOC_METERS = 0x0c0,
1167 SUNI_CPPM_CHG_OF_CPPM_PERF_METR = 0x0c4,
1168 SUNI_CPPM_B1_ERR_CNT_LSB = 0x0c8,
1169 SUNI_CPPM_B1_ERR_CNT_MSB = 0x0cc,
1170 SUNI_CPPM_FRAMING_ERR_CNT_LSB = 0x0d0,
1171 SUNI_CPPM_FRAMING_ERR_CNT_MSB = 0x0d4,
1172 SUNI_CPPM_FEBE_CNT_LSB = 0x0d8,
1173 SUNI_CPPM_FEBE_CNT_MSB = 0x0dc,
1174 SUNI_CPPM_HCS_ERR_CNT_LSB = 0x0e0,
1175 SUNI_CPPM_HCS_ERR_CNT_MSB = 0x0e4,
1176 SUNI_CPPM_IDLE_UN_CELL_CNT_LSB = 0x0e8,
1177 SUNI_CPPM_IDLE_UN_CELL_CNT_MSB = 0x0ec,
1178 SUNI_CPPM_RCV_CELL_CNT_LSB = 0x0f0,
1179 SUNI_CPPM_RCV_CELL_CNT_MSB = 0x0f4,
1180 SUNI_CPPM_XMIT_CELL_CNT_LSB = 0x0f8,
1181 SUNI_CPPM_XMIT_CELL_CNT_MSB = 0x0fc,
1182 SUNI_RXCP_CTRL = 0x100,
1183 SUNI_RXCP_FCTRL = 0x104,
1184 SUNI_RXCP_INTR_EN_STS = 0x108,
1185 SUNI_RXCP_IDLE_PAT_H1 = 0x10c,
1186 SUNI_RXCP_IDLE_PAT_H2 = 0x110,
1187 SUNI_RXCP_IDLE_PAT_H3 = 0x114,
1188 SUNI_RXCP_IDLE_PAT_H4 = 0x118,
1189 SUNI_RXCP_IDLE_MASK_H1 = 0x11c,
1190 SUNI_RXCP_IDLE_MASK_H2 = 0x120,
1191 SUNI_RXCP_IDLE_MASK_H3 = 0x124,
1192 SUNI_RXCP_IDLE_MASK_H4 = 0x128,
1193 SUNI_RXCP_CELL_PAT_H1 = 0x12c,
1194 SUNI_RXCP_CELL_PAT_H2 = 0x130,
1195 SUNI_RXCP_CELL_PAT_H3 = 0x134,
1196 SUNI_RXCP_CELL_PAT_H4 = 0x138,
1197 SUNI_RXCP_CELL_MASK_H1 = 0x13c,
1198 SUNI_RXCP_CELL_MASK_H2 = 0x140,
1199 SUNI_RXCP_CELL_MASK_H3 = 0x144,
1200 SUNI_RXCP_CELL_MASK_H4 = 0x148,
1201 SUNI_RXCP_HCS_CS = 0x14c,
1202 SUNI_RXCP_LCD_CNT_THRESHOLD = 0x150,
1203 /* SUNI_RESERVED3 (0x57 - 0x54) */
1204 SUNI_TXCP_CTRL = 0x160,
1205 SUNI_TXCP_INTR_EN_STS = 0x164,
1206 SUNI_TXCP_IDLE_PAT_H1 = 0x168,
1207 SUNI_TXCP_IDLE_PAT_H2 = 0x16c,
1208 SUNI_TXCP_IDLE_PAT_H3 = 0x170,
1209 SUNI_TXCP_IDLE_PAT_H4 = 0x174,
1210 SUNI_TXCP_IDLE_PAT_H5 = 0x178,
1211 SUNI_TXCP_IDLE_PAYLOAD = 0x17c,
1212 SUNI_E3_FRM_FRAM_OPTIONS = 0x180,
1213 SUNI_E3_FRM_MAINT_OPTIONS = 0x184,
1214 SUNI_E3_FRM_FRAM_INTR_ENBL = 0x188,
1215 SUNI_E3_FRM_FRAM_INTR_IND_STAT = 0x18c,
1216 SUNI_E3_FRM_MAINT_INTR_ENBL = 0x190,
1217 SUNI_E3_FRM_MAINT_INTR_IND = 0x194,
1218 SUNI_E3_FRM_MAINT_STAT = 0x198,
1219 SUNI_RESERVED4 = 0x19c,
1220 SUNI_E3_TRAN_FRAM_OPTIONS = 0x1a0,
1221 SUNI_E3_TRAN_STAT_DIAG_OPTIONS = 0x1a4,
1222 SUNI_E3_TRAN_BIP_8_ERR_MASK = 0x1a8,
1223 SUNI_E3_TRAN_MAINT_ADAPT_OPTS = 0x1ac,
1224 SUNI_TTB_CTRL = 0x1b0,
1225 SUNI_TTB_TRAIL_TRACE_ID_STAT = 0x1b4,
1226 SUNI_TTB_IND_ADDR = 0x1b8,
1227 SUNI_TTB_IND_DATA = 0x1bc,
1228 SUNI_TTB_EXP_PAYLOAD_TYPE = 0x1c0,
1229 SUNI_TTB_PAYLOAD_TYPE_CTRL_STAT = 0x1c4,
1230 /* SUNI_PAD5 (0x7f - 0x71) */
1231 SUNI_MASTER_TEST = 0x200,
1232 /* SUNI_PAD6 (0xff - 0x80) */
1236 #define SUNI_PM7345 0x20 /* Suni chip type */
1237 #define SUNI_PM5346 0x30 /* Suni chip type */
1241 #define SUNI_PM7345_CLB 0x01 /* Cell loopback */
1242 #define SUNI_PM7345_PLB 0x02 /* Payload loopback */
1243 #define SUNI_PM7345_DLB 0x04 /* Diagnostic loopback */
1244 #define SUNI_PM7345_LLB 0x80 /* Line loopback */
1245 #define SUNI_PM7345_E3ENBL 0x40 /* E3 enable bit */
1246 #define SUNI_PM7345_LOOPT 0x10 /* LOOPT enable bit */
1247 #define SUNI_PM7345_FIFOBP 0x20 /* FIFO bypass */
1248 #define SUNI_PM7345_FRMRBP 0x08 /* Framer bypass */
1252 #define SUNI_DS3_COFAE 0x80 /* Enable change of frame align */
1253 #define SUNI_DS3_REDE 0x40 /* Enable DS3 RED state intr */
1254 #define SUNI_DS3_CBITE 0x20 /* Enable Appl ID channel intr */
1255 #define SUNI_DS3_FERFE 0x10 /* Enable Far End Receive Failure intr*/
1256 #define SUNI_DS3_IDLE 0x08 /* Enable Idle signal intr */
1257 #define SUNI_DS3_AISE 0x04 /* Enable Alarm Indication signal intr*/
1258 #define SUNI_DS3_OOFE 0x02 /* Enable Out of frame intr */
1259 #define SUNI_DS3_LOSE 0x01 /* Enable Loss of signal intr */
1264 #define SUNI_DS3_ACE 0x80 /* Additional Configuration Reg */
1265 #define SUNI_DS3_REDV 0x40 /* DS3 RED state */
1266 #define SUNI_DS3_CBITV 0x20 /* Application ID channel state */
1267 #define SUNI_DS3_FERFV 0x10 /* Far End Receive Failure state*/
1268 #define SUNI_DS3_IDLV 0x08 /* Idle signal state */
1269 #define SUNI_DS3_AISV 0x04 /* Alarm Indication signal state*/
1270 #define SUNI_DS3_OOFV 0x02 /* Out of frame state */
1271 #define SUNI_DS3_LOSV 0x01 /* Loss of signal state */
1276 #define SUNI_E3_CZDI 0x40 /* Consecutive Zeros indicator */
1277 #define SUNI_E3_LOSI 0x20 /* Loss of signal intr status */
1278 #define SUNI_E3_LCVI 0x10 /* Line code violation intr */
1279 #define SUNI_E3_COFAI 0x08 /* Change of frame align intr */
1280 #define SUNI_E3_OOFI 0x04 /* Out of frame intr status */
1281 #define SUNI_E3_LOS 0x02 /* Loss of signal state */
1282 #define SUNI_E3_OOF 0x01 /* Out of frame state */
1287 #define SUNI_E3_AISD 0x80 /* Alarm Indication signal state*/
1288 #define SUNI_E3_FERF_RAI 0x40 /* FERF/RAI indicator */
1289 #define SUNI_E3_FEBE 0x20 /* Far End Block Error indicator*/
1294 #define SUNI_DS3_HCSPASS 0x80 /* Pass cell with HEC errors */
1295 #define SUNI_DS3_HCSDQDB 0x40 /* Control octets in HCS calc */
1296 #define SUNI_DS3_HCSADD 0x20 /* Add coset poly */
1297 #define SUNI_DS3_HCK 0x10 /* Control FIFO data path integ chk*/
1298 #define SUNI_DS3_BLOCK 0x08 /* Enable cell filtering */
1299 #define SUNI_DS3_DSCR 0x04 /* Disable payload descrambling */
1300 #define SUNI_DS3_OOCDV 0x02 /* Cell delineation state */
1301 #define SUNI_DS3_FIFORST 0x01 /* Cell FIFO reset */
1306 #define SUNI_DS3_OOCDE 0x80 /* Intr enable, change in CDS */
1307 #define SUNI_DS3_HCSE 0x40 /* Intr enable, corr HCS errors */
1308 #define SUNI_DS3_FIFOE 0x20 /* Intr enable, unco HCS errors */
1309 #define SUNI_DS3_OOCDI 0x10 /* SYNC state */
1310 #define SUNI_DS3_UHCSI 0x08 /* Uncorr. HCS errors detected */
1311 #define SUNI_DS3_COCAI 0x04 /* Corr. HCS errors detected */
1312 #define SUNI_DS3_FOVRI 0x02 /* FIFO overrun */
1313 #define SUNI_DS3_FUDRI 0x01 /* FIFO underrun */
1318 #define MEM_SIZE_MASK 0x000F /* mask of 4 bits defining memory size*/
1319 #define MEM_SIZE_128K 0x0000 /* board has 128k buffer */
1320 #define MEM_SIZE_512K 0x0001 /* board has 512K of buffer */
1321 #define MEM_SIZE_1M 0x0002 /* board has 1M of buffer */
1322 /* 0x3 to 0xF are reserved for future */
1324 #define FE_MASK 0x00F0 /* mask of 4 bits defining FE type */
1325 #define FE_MULTI_MODE 0x0000 /* 155 MBit multimode fiber */
1326 #define FE_SINGLE_MODE 0x0010 /* 155 MBit single mode laser */
1327 #define FE_UTP_OPTION 0x0020 /* 155 MBit UTP front end */
1346 #define EXTEND 0x100
1347 #define IAWRITE 0x140
1348 #define IAREAD 0x180
1349 #define ERASE 0x1c0
1351 #define EWDS 0x00
1352 #define WRAL 0x10
1353 #define ERAL 0x20
1354 #define EWEN 0x30
1361 #define NVCE 0x02
1362 #define NVSK 0x01
1363 #define NVDO 0x08
1364 #define NVDI 0x04
1408 for (i=0; i<CMD_LEN; i++) { \
1409 NVRAM_CLKOUT((c & (1 << (CMD_LEN - 1))) ? 1 : 0); \
1425 * a 1 or 0, or the clockout operation is undefined
1431 CFG_OR((bitval) ? NVDI : 0); \
1438 * clock the data bit in and return a 1 or 0, depending on the value
1448 value = (_t & NVDO) ? 1 : 0; \