Lines Matching defs:_ffredn_t
641 typedef struct _ffredn_t { struct
642 ffreg_t idlehead_high; /* Idle cell header (high) */
643 ffreg_t idlehead_low; /* Idle cell header (low) */
644 ffreg_t maxrate; /* Maximum rate */
645 ffreg_t stparms; /* Traffic Management Parameters */
646 ffreg_t abrubr_abr; /* ABRUBR Priority Byte 1, TCR Byte 0 */
647 ffreg_t rm_type; /* */
648 u_int filler5[0x17 - 0x06];
649 ffreg_t cmd_reg; /* Command register */
650 u_int filler18[0x20 - 0x18];
651 ffreg_t cbr_base; /* CBR Pointer Base */
652 ffreg_t vbr_base; /* VBR Pointer Base */
653 ffreg_t abr_base; /* ABR Pointer Base */
654 ffreg_t ubr_base; /* UBR Pointer Base */
655 u_int filler24;
656 ffreg_t vbrwq_base; /* VBR Wait Queue Base */
657 ffreg_t abrwq_base; /* ABR Wait Queue Base */
658 ffreg_t ubrwq_base; /* UBR Wait Queue Base */
659 ffreg_t vct_base; /* Main VC Table Base */
660 ffreg_t vcte_base; /* Extended Main VC Table Base */
661 u_int filler2a[0x2C - 0x2A];
662 ffreg_t cbr_tab_beg; /* CBR Table Begin */
663 ffreg_t cbr_tab_end; /* CBR Table End */
664 ffreg_t cbr_pointer; /* CBR Pointer */
665 u_int filler2f[0x30 - 0x2F];
666 ffreg_t prq_st_adr; /* Packet Ready Queue Start Address */
667 ffreg_t prq_ed_adr; /* Packet Ready Queue End Address */
668 ffreg_t prq_rd_ptr; /* Packet Ready Queue read pointer */
669 ffreg_t prq_wr_ptr; /* Packet Ready Queue write pointer */
670 ffreg_t tcq_st_adr; /* Transmit Complete Queue Start Address*/
671 ffreg_t tcq_ed_adr; /* Transmit Complete Queue End Address */
672 ffreg_t tcq_rd_ptr; /* Transmit Complete Queue read pointer */
673 ffreg_t tcq_wr_ptr; /* Transmit Complete Queue write pointer*/
674 u_int filler38[0x40 - 0x38];
675 ffreg_t queue_base; /* Base address for PRQ and TCQ */
676 ffreg_t desc_base; /* Base address of descriptor table */
677 u_int filler42[0x45 - 0x42];
678 ffreg_t mode_reg_0; /* Mode register 0 */
679 ffreg_t mode_reg_1; /* Mode register 1 */
680 ffreg_t intr_status_reg;/* Interrupt Status register */
681 ffreg_t mask_reg; /* Mask Register */
682 ffreg_t cell_ctr_high1; /* Total cell transfer count (high) */
683 ffreg_t cell_ctr_lo1; /* Total cell transfer count (low) */
684 ffreg_t state_reg; /* Status register */
685 u_int filler4c[0x58 - 0x4c];
686 ffreg_t curr_desc_num; /* Contains the current descriptor num */
687 ffreg_t next_desc; /* Next descriptor */
688 ffreg_t next_vc; /* Next VC */
689 u_int filler5b[0x5d - 0x5b];
690 ffreg_t present_slot_cnt;/* Present slot count */
691 u_int filler5e[0x6a - 0x5e];
692 ffreg_t new_desc_num; /* New descriptor number */
693 ffreg_t new_vc; /* New VC */
694 ffreg_t sched_tbl_ptr; /* Schedule table pointer */
695 ffreg_t vbrwq_wptr; /* VBR wait queue write pointer */
696 ffreg_t vbrwq_rptr; /* VBR wait queue read pointer */
697 ffreg_t abrwq_wptr; /* ABR wait queue write pointer */
698 ffreg_t abrwq_rptr; /* ABR wait queue read pointer */
699 ffreg_t ubrwq_wptr; /* UBR wait queue write pointer */
700 ffreg_t ubrwq_rptr; /* UBR wait queue read pointer */
701 ffreg_t cbr_vc; /* CBR VC */
702 ffreg_t vbr_sb_vc; /* VBR SB VC */
703 ffreg_t abr_sb_vc; /* ABR SB VC */
704 ffreg_t ubr_sb_vc; /* UBR SB VC */
705 ffreg_t vbr_next_link; /* VBR next link */
706 ffreg_t abr_next_link; /* ABR next link */
707 ffreg_t ubr_next_link; /* UBR next link */
708 u_int filler7a[0x7c-0x7a];
709 ffreg_t out_rate_head; /* Out of rate head */
710 u_int filler7d[0xca-0x7d]; /* pad out to full address space */
711 ffreg_t cell_ctr_high1_nc;/* Total cell transfer count (high) */
712 ffreg_t cell_ctr_lo1_nc;/* Total cell transfer count (low) */
713 u_int fillercc[0x100-0xcc]; /* pad out to full address space */