39 	QS_HCF_CNFG3		= 0x0003, /* host configuration offset */
40 	QS_HID_HPHY		= 0x0004, /* host physical interface info */
41 	QS_HCT_CTRL		= 0x00e4, /* global interrupt mask offset */
42 	QS_HST_SFF		= 0x0100, /* host status fifo offset */
43 	QS_HVS_SERD3		= 0x0393, /* PHY enable offset */
47 	QS_CNFG3_GSRST		= 0x01,     /* global chip reset */
48 	QS_SERD3_PHY_ENA	= 0xf0,     /* PHY detection ENAble*/
51 	QS_CCF_CPBA		= 0x0710, /* chan CPB base address */
52 	QS_CCF_CSEP		= 0x0718, /* chan CPB separation factor */
53 	QS_CFC_HUFT		= 0x0800, /* host upstream fifo threshold */
54 	QS_CFC_HDFT		= 0x0804, /* host downstream fifo threshold */
55 	QS_CFC_DUFT		= 0x0808, /* dev upstream fifo threshold */
56 	QS_CFC_DDFT		= 0x080c, /* dev downstream fifo threshold */
57 	QS_CCT_CTR0		= 0x0900, /* chan control-0 offset */
58 	QS_CCT_CTR1		= 0x0901, /* chan control-1 offset */
59 	QS_CCT_CFF		= 0x0a00, /* chan command fifo offset */
66 	QS_CCF_RUN_PKT		= 0x107,      /* RUN a new dma PKT */
69 	QS_HCB_HDR		= 0x01,   /* Host Control Block header */
70 	QS_DCB_HDR		= 0x02,   /* Device Control Block header */
73 	QS_HF_DIRO		= (1 << 0),   /* data DIRection Out */
83 	board_2068_idx		= 0,	/* QStor 4-port SATA/RAID */
87 	QS_DMA_BOUNDARY		= ~0UL
149 	{ PCI_VDEVICE(PDC, 0x2068), board_2068_idx },
173 	u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);  in qs_enter_reg_mode()
183 	u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);  in qs_reset_channel_logic()
194 	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */  in qs_freeze()
219 	return 0;  in qs_scr_read()
233 	return 0;  in qs_scr_write()
280 	buf[ 0] = QS_HCB_HDR;  in qs_qc_prep()
292 	ata_tf_to_fis(&qc->tf, 0, 1, &buf[32]);  in qs_qc_prep()
300 	u8 __iomem *chan = qs_mmio_base(ap->host) + (ap->port_no * 0x4000);  in qs_packet_start()
316 		return 0;  in qs_qc_issue()
341 		ata_ehi_push_desc(ehi, "status 0x%02X", status);  in qs_do_or_die()
352 	unsigned int handled = 0;  in qs_intr_pkt()
359 		u8 sEVLD = (sff1 >> 30) & 0x01;	/* valid flag */  in qs_intr_pkt()
364 			u8 sHST = sff1 & 0x3f;	/* host status */  in qs_intr_pkt()
365 			unsigned int port_no = (sff1 >> 8) & 0x03;  in qs_intr_pkt()
378 				case 0: /* successful CPB */  in qs_intr_pkt()
394 	unsigned int handled = 0, port_no;  in qs_intr_mmio()
396 	for (port_no = 0; port_no < host->n_ports; ++port_no) {  in qs_intr_mmio()
428 	unsigned int handled = 0;  in qs_intr()
441 	port->data_addr		= base + 0x400;  in qs_ata_setup_port()
443 	port->feature_addr	= base + 0x408; /* hob_feature = 0x409 */  in qs_ata_setup_port()
444 	port->nsect_addr	= base + 0x410; /* hob_nsect   = 0x411 */  in qs_ata_setup_port()
445 	port->lbal_addr		= base + 0x418; /* hob_lbal    = 0x419 */  in qs_ata_setup_port()
446 	port->lbam_addr		= base + 0x420; /* hob_lbam    = 0x421 */  in qs_ata_setup_port()
447 	port->lbah_addr		= base + 0x428; /* hob_lbah    = 0x429 */  in qs_ata_setup_port()
448 	port->device_addr	= base + 0x430;  in qs_ata_setup_port()
450 	port->command_addr	= base + 0x438;  in qs_ata_setup_port()
452 	port->ctl_addr		= base + 0x440;  in qs_ata_setup_port()
453 	port->scr_addr		= base + 0xc00;  in qs_ata_setup_port()
461 	void __iomem *chan = mmio_base + (ap->port_no * 0x4000);  in qs_port_start()
477 	return 0;  in qs_port_start()
484 	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */  in qs_host_stop()
493 	writeb(0, mmio_base + QS_HCT_CTRL); /* disable host interrupts */  in qs_host_init()
497 	for (port_no = 0; port_no < host->n_ports; ++port_no) {  in qs_host_init()
498 		u8 __iomem *chan = mmio_base + (port_no * 0x4000);  in qs_host_init()
505 	for (port_no = 0; port_no < host->n_ports; ++port_no) {  in qs_host_init()
506 		u8 __iomem *chan = mmio_base + (port_no * 0x4000);  in qs_host_init()
560 	if ((pci_resource_flags(pdev, QS_MMIO_BAR) & IORESOURCE_MEM) == 0)  in qs_ata_init_one()
572 	for (port_no = 0; port_no < host->n_ports; ++port_no) {  in qs_ata_init_one()
574 		unsigned int offset = port_no * 0x4000;  in qs_ata_init_one()