103 	NV_ADMA_CTL			= 0x40,  enumerator
618 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_register_mode()
619 	writew(tmp & ~NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);  in nv_adma_register_mode()
648 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_mode()
649 	writew(tmp | NV_ADMA_CTL_GO, mmio + NV_ADMA_CTL);  in nv_adma_mode()
1031 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_freeze()
1033 		mmio + NV_ADMA_CTL);  in nv_adma_freeze()
1034 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_freeze()
1049 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_thaw()
1051 		mmio + NV_ADMA_CTL);  in nv_adma_thaw()
1052 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_thaw()
1176 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1178 		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1180 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1181 	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1182 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_start()
1184 	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_start()
1185 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_start()
1195 	writew(0, mmio + NV_ADMA_CTL);  in nv_adma_port_stop()
1211 	writew(0, mmio + NV_ADMA_CTL);  in nv_adma_port_suspend()
1236 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1238 		NV_ADMA_CTL_HOTPLUG_IEN, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1240 	tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1241 	writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1242 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_resume()
1244 	writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_port_resume()
1245 	readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_port_resume()
1673 		tmp = readw(mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1674 		writew(tmp | NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1675 		readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_error_handler()
1677 		writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);  in nv_adma_error_handler()
1678 		readw(mmio + NV_ADMA_CTL);	/* flush posted write */  in nv_adma_error_handler()