Lines Matching +full:rx +full:- +full:max +full:- +full:burst +full:- +full:prd
1 // SPDX-License-Identifier: GPL-2.0-only
3 * sata_mv.c - Marvell SATA support
5 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
12 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
18 * --> Develop a low-power-consumption strategy, and implement it.
20 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
22 * --> [Experiment, Marvell value added] Is it possible to use target
23 * mode to cross-connect two Linux boxes with Marvell cards? If so,
31 * 80x1-B2 errata PCI#11:
34 * should be careful to insert those cards only onto PCI-X bus #0,
47 #include <linux/dma-mapping.h>
95 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
97 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
103 * Per-chip ("all ports") interrupt coalescing feature.
133 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
144 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
147 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
148 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
164 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
165 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
166 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
172 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
173 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
203 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
209 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
216 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
217 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
229 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
230 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
231 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
242 * Per-HC (Host-Controller) interrupt coalescing feature.
266 LTMODE = 0x30c, /* requires read-after-write */
272 PHY_MODE4 = 0x314, /* requires read-after-write */
306 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
309 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
311 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
312 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
317 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
322 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
323 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
331 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
335 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
337 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
397 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
412 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
413 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
425 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
438 #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
439 #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
440 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
441 #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
442 #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
449 * we need on /length/ in mv_fill-sg().
507 * when switching between EDMA and non-EDMA modes.
556 * all the clock operations become no-ops (see clk.h).
568 * alignment for hardware-accessed data structures,
670 .can_queue = MV_MAX_Q_DEPTH - 1,
847 * This is hot-path stuff, so not a function.
891 struct mv_host_priv *hpriv = host->private_data; in mv_host_base()
892 return hpriv->base; in mv_host_base()
897 return mv_port_base(mv_host_base(ap->host), ap->port_no); in mv_ap_base()
906 * mv_save_cached_regs - (re-)initialize cached port registers
918 struct mv_port_priv *pp = ap->private_data; in mv_save_cached_regs()
920 pp->cached.fiscfg = readl(port_mmio + FISCFG); in mv_save_cached_regs()
921 pp->cached.ltmode = readl(port_mmio + LTMODE); in mv_save_cached_regs()
922 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); in mv_save_cached_regs()
923 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); in mv_save_cached_regs()
927 * mv_write_cached_reg - write to a cached port register
941 * Workaround for 88SX60x1-B2 FEr SATA#13: in mv_write_cached_reg()
942 * Read-after-write is needed to prevent generating 64-bit in mv_write_cached_reg()
947 * +1 usec read-after-write delay for unaffected registers. in mv_write_cached_reg()
970 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ in mv_set_edma_ptrs()
971 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; in mv_set_edma_ptrs()
973 WARN_ON(pp->crqb_dma & 0x3ff); in mv_set_edma_ptrs()
974 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); in mv_set_edma_ptrs()
975 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, in mv_set_edma_ptrs()
982 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ in mv_set_edma_ptrs()
983 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; in mv_set_edma_ptrs()
985 WARN_ON(pp->crpb_dma & 0xff); in mv_set_edma_ptrs()
986 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); in mv_set_edma_ptrs()
988 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, in mv_set_edma_ptrs()
1006 writelfl(mask, hpriv->main_irq_mask_addr); in mv_write_main_irq_mask()
1012 struct mv_host_priv *hpriv = host->private_data; in mv_set_main_irq_mask()
1015 old_mask = hpriv->main_irq_mask; in mv_set_main_irq_mask()
1018 hpriv->main_irq_mask = new_mask; in mv_set_main_irq_mask()
1026 unsigned int shift, hardport, port = ap->port_no; in mv_enable_port_irqs()
1033 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); in mv_enable_port_irqs()
1040 struct mv_host_priv *hpriv = ap->host->private_data; in mv_clear_and_enable_port_irqs()
1041 int hardport = mv_hardport_from_port(ap->port_no); in mv_clear_and_enable_port_irqs()
1043 mv_host_base(ap->host), ap->port_no); in mv_clear_and_enable_port_irqs()
1063 struct mv_host_priv *hpriv = host->private_data; in mv_set_irq_coalescing()
1064 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_set_irq_coalescing()
1067 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; in mv_set_irq_coalescing()
1083 spin_lock_irqsave(&host->lock, flags); in mv_set_irq_coalescing()
1119 spin_unlock_irqrestore(&host->lock, flags); in mv_set_irq_coalescing()
1123 * mv_start_edma - Enable eDMA engine
1137 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { in mv_start_edma()
1138 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); in mv_start_edma()
1142 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { in mv_start_edma()
1143 struct mv_host_priv *hpriv = ap->host->private_data; in mv_start_edma()
1151 pp->pp_flags |= MV_PP_FLAG_EDMA_EN; in mv_start_edma()
1166 * with two drives in-use. So we use the 15msec value above in mv_wait_for_edma_empty_idle()
1179 * mv_stop_edma_engine - Disable eDMA engine
1193 for (i = 10000; i > 0; i--) { in mv_stop_edma_engine()
1199 return -EIO; in mv_stop_edma_engine()
1205 struct mv_port_priv *pp = ap->private_data; in mv_stop_edma()
1208 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) in mv_stop_edma()
1210 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_stop_edma()
1214 err = -EIO; in mv_stop_edma()
1227 o += scnprintf(linebuf + o, sizeof(linebuf) - o, in mv_dump_mem()
1245 o += snprintf(linebuf + o, sizeof(linebuf) - o, in mv_dump_pci_cfg()
1249 dev_dbg(&pdev->dev, "%s: %02x: %s\n", in mv_dump_pci_cfg()
1264 dev_dbg(&pdev->dev, in mv_dump_all_regs()
1265 "%s: All registers for port(s) %u-%u:\n", __func__, in mv_dump_all_regs()
1266 start_port, num_ports > 1 ? num_ports - 1 : start_port); in mv_dump_all_regs()
1268 dev_dbg(&pdev->dev, "%s: PCI config space regs:\n", __func__); in mv_dump_all_regs()
1271 dev_dbg(&pdev->dev, "%s: PCI regs:\n", __func__); in mv_dump_all_regs()
1272 mv_dump_mem(&pdev->dev, mmio_base+0xc00, 0x3c); in mv_dump_all_regs()
1273 mv_dump_mem(&pdev->dev, mmio_base+0xd00, 0x34); in mv_dump_all_regs()
1274 mv_dump_mem(&pdev->dev, mmio_base+0xf00, 0x4); in mv_dump_all_regs()
1275 mv_dump_mem(&pdev->dev, mmio_base+0x1d00, 0x6c); in mv_dump_all_regs()
1278 dev_dbg(&pdev->dev, "%s: HC regs (HC %i):\n", __func__, hc); in mv_dump_all_regs()
1279 mv_dump_mem(&pdev->dev, hc_base, 0x1c); in mv_dump_all_regs()
1283 dev_dbg(&pdev->dev, "%s: EDMA regs (port %i):\n", __func__, p); in mv_dump_all_regs()
1284 mv_dump_mem(&pdev->dev, port_base, 0x54); in mv_dump_all_regs()
1285 dev_dbg(&pdev->dev, "%s: SATA regs (port %i):\n", __func__, p); in mv_dump_all_regs()
1286 mv_dump_mem(&pdev->dev, port_base+0x300, 0x60); in mv_dump_all_regs()
1315 *val = readl(mv_ap_base(link->ap) + ofs); in mv_scr_read()
1318 return -EINVAL; in mv_scr_read()
1326 void __iomem *addr = mv_ap_base(link->ap) + ofs; in mv_scr_write()
1327 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv_scr_write()
1345 if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) { in mv_scr_write()
1347 mv_ap_base(link->ap) + LP_PHY_CTL; in mv_scr_write()
1367 return -EINVAL; in mv_scr_write()
1373 * Deal with Gen-II ("mv6") hardware quirks/restrictions: in mv6_dev_config()
1375 * Gen-II does not support NCQ over a port multiplier in mv6_dev_config()
1376 * (no FIS-based switching). in mv6_dev_config()
1378 if (adev->flags & ATA_DFLAG_NCQ) { in mv6_dev_config()
1379 if (sata_pmp_attached(adev->link->ap)) { in mv6_dev_config()
1380 adev->flags &= ~ATA_DFLAG_NCQ; in mv6_dev_config()
1382 "NCQ disabled for command-based switching\n"); in mv6_dev_config()
1389 struct ata_link *link = qc->dev->link; in mv_qc_defer()
1390 struct ata_port *ap = link->ap; in mv_qc_defer()
1391 struct mv_port_priv *pp = ap->private_data; in mv_qc_defer()
1395 * for NCQ and/or FIS-based switching. in mv_qc_defer()
1397 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) in mv_qc_defer()
1403 * or a non-NCQ command in NCQ mode. in mv_qc_defer()
1408 if (unlikely(ap->excl_link)) { in mv_qc_defer()
1409 if (link == ap->excl_link) { in mv_qc_defer()
1410 if (ap->nr_active_links) in mv_qc_defer()
1412 qc->flags |= ATA_QCFLAG_CLEAR_EXCL; in mv_qc_defer()
1421 if (ap->nr_active_links == 0) in mv_qc_defer()
1430 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && in mv_qc_defer()
1431 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { in mv_qc_defer()
1432 if (ata_is_ncq(qc->tf.protocol)) in mv_qc_defer()
1435 ap->excl_link = link; in mv_qc_defer()
1445 struct mv_port_priv *pp = ap->private_data; in mv_config_fbs()
1448 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; in mv_config_fbs()
1449 u32 ltmode, *old_ltmode = &pp->cached.ltmode; in mv_config_fbs()
1450 u32 haltcond, *old_haltcond = &pp->cached.haltcond; in mv_config_fbs()
1474 struct mv_host_priv *hpriv = ap->host->private_data; in mv_60x1_errata_sata25()
1478 old = readl(hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1484 writel(new, hpriv->base + GPIO_PORT_CTL); in mv_60x1_errata_sata25()
1488 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1493 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1501 struct mv_port_priv *pp = ap->private_data; in mv_bmdma_enable_iie()
1502 u32 new, *old = &pp->cached.unknown_rsvd; in mv_bmdma_enable_iie()
1527 struct ata_host *host = ap->host; in mv_soc_led_blink_enable()
1528 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_enable()
1532 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) in mv_soc_led_blink_enable()
1534 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_enable()
1535 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); in mv_soc_led_blink_enable()
1542 struct ata_host *host = ap->host; in mv_soc_led_blink_disable()
1543 struct mv_host_priv *hpriv = host->private_data; in mv_soc_led_blink_disable()
1548 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) in mv_soc_led_blink_disable()
1551 /* disable led-blink only if no ports are using NCQ */ in mv_soc_led_blink_disable()
1552 for (port = 0; port < hpriv->n_ports; port++) { in mv_soc_led_blink_disable()
1553 struct ata_port *this_ap = host->ports[port]; in mv_soc_led_blink_disable()
1554 struct mv_port_priv *pp = this_ap->private_data; in mv_soc_led_blink_disable()
1556 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) in mv_soc_led_blink_disable()
1560 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; in mv_soc_led_blink_disable()
1561 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); in mv_soc_led_blink_disable()
1569 struct mv_port_priv *pp = ap->private_data; in mv_edma_cfg()
1570 struct mv_host_priv *hpriv = ap->host->private_data; in mv_edma_cfg()
1573 /* set up non-NCQ EDMA configuration */ in mv_edma_cfg()
1575 pp->pp_flags &= in mv_edma_cfg()
1579 cfg |= (1 << 8); /* enab config burst size mask */ in mv_edma_cfg()
1590 * The chip can use FBS with non-NCQ, if we allow it, in mv_edma_cfg()
1593 * So disallow non-NCQ FBS for now. in mv_edma_cfg()
1600 pp->pp_flags |= MV_PP_FLAG_FBS_EN; in mv_edma_cfg()
1601 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ in mv_edma_cfg()
1604 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ in mv_edma_cfg()
1606 cfg |= (1 << 22); /* enab 4-entry host queue cache */ in mv_edma_cfg()
1610 if (hpriv->hp_flags & MV_HP_CUT_THROUGH) in mv_edma_cfg()
1611 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ in mv_edma_cfg()
1624 pp->pp_flags |= MV_PP_FLAG_NCQ_EN; in mv_edma_cfg()
1632 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_free_dma_mem()
1633 struct mv_port_priv *pp = ap->private_data; in mv_port_free_dma_mem()
1636 if (pp->crqb) { in mv_port_free_dma_mem()
1637 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); in mv_port_free_dma_mem()
1638 pp->crqb = NULL; in mv_port_free_dma_mem()
1640 if (pp->crpb) { in mv_port_free_dma_mem()
1641 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); in mv_port_free_dma_mem()
1642 pp->crpb = NULL; in mv_port_free_dma_mem()
1649 if (pp->sg_tbl[tag]) { in mv_port_free_dma_mem()
1651 dma_pool_free(hpriv->sg_tbl_pool, in mv_port_free_dma_mem()
1652 pp->sg_tbl[tag], in mv_port_free_dma_mem()
1653 pp->sg_tbl_dma[tag]); in mv_port_free_dma_mem()
1654 pp->sg_tbl[tag] = NULL; in mv_port_free_dma_mem()
1660 * mv_port_start - Port specific init/start routine.
1671 struct device *dev = ap->host->dev; in mv_port_start()
1672 struct mv_host_priv *hpriv = ap->host->private_data; in mv_port_start()
1679 return -ENOMEM; in mv_port_start()
1680 ap->private_data = pp; in mv_port_start()
1682 pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); in mv_port_start()
1683 if (!pp->crqb) in mv_port_start()
1684 return -ENOMEM; in mv_port_start()
1686 pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); in mv_port_start()
1687 if (!pp->crpb) in mv_port_start()
1691 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) in mv_port_start()
1692 ap->flags |= ATA_FLAG_AN; in mv_port_start()
1699 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, in mv_port_start()
1700 GFP_KERNEL, &pp->sg_tbl_dma[tag]); in mv_port_start()
1701 if (!pp->sg_tbl[tag]) in mv_port_start()
1704 pp->sg_tbl[tag] = pp->sg_tbl[0]; in mv_port_start()
1705 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; in mv_port_start()
1709 spin_lock_irqsave(ap->lock, flags); in mv_port_start()
1712 spin_unlock_irqrestore(ap->lock, flags); in mv_port_start()
1718 return -ENOMEM; in mv_port_start()
1722 * mv_port_stop - Port specific cleanup/stop routine.
1734 spin_lock_irqsave(ap->lock, flags); in mv_port_stop()
1737 spin_unlock_irqrestore(ap->lock, flags); in mv_port_stop()
1742 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1752 struct mv_port_priv *pp = qc->ap->private_data; in mv_fill_sg()
1757 mv_sg = pp->sg_tbl[qc->hw_tag]; in mv_fill_sg()
1758 for_each_sg(qc->sg, sg, qc->n_elem, si) { in mv_fill_sg()
1767 len = 0x10000 - offset; in mv_fill_sg()
1769 mv_sg->addr = cpu_to_le32(addr & 0xffffffff); in mv_fill_sg()
1770 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); in mv_fill_sg()
1771 mv_sg->flags_size = cpu_to_le32(len & 0xffff); in mv_fill_sg()
1772 mv_sg->reserved = 0; in mv_fill_sg()
1774 sg_len -= len; in mv_fill_sg()
1783 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); in mv_fill_sg()
1795 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1800 * after libata-sff handles the bmdma interrupts.
1808 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1820 struct scsi_cmnd *scmd = qc->scsicmd; in mv_check_atapi_dma()
1823 switch (scmd->cmnd[0]) { in mv_check_atapi_dma()
1836 return -EOPNOTSUPP; /* use PIO instead */ in mv_check_atapi_dma()
1840 * mv_bmdma_setup - Set up BMDMA transaction
1848 struct ata_port *ap = qc->ap; in mv_bmdma_setup()
1850 struct mv_port_priv *pp = ap->private_data; in mv_bmdma_setup()
1857 /* load PRD table addr. */ in mv_bmdma_setup()
1858 writel((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16, in mv_bmdma_setup()
1860 writelfl(pp->sg_tbl_dma[qc->hw_tag], in mv_bmdma_setup()
1864 ap->ops->sff_exec_command(ap, &qc->tf); in mv_bmdma_setup()
1868 * mv_bmdma_start - Start a BMDMA transaction
1876 struct ata_port *ap = qc->ap; in mv_bmdma_start()
1878 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); in mv_bmdma_start()
1886 * mv_bmdma_stop_ap - Stop BMDMA transfer
1905 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ in mv_bmdma_stop_ap()
1912 mv_bmdma_stop_ap(qc->ap); in mv_bmdma_stop()
1916 * mv_bmdma_status - Read BMDMA status
1946 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY) in mv_bmdma_status()
1956 struct ata_taskfile *tf = &qc->tf; in mv_rw_multi_errata_sata24()
1970 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { in mv_rw_multi_errata_sata24()
1971 if (qc->dev->multi_count > 7) { in mv_rw_multi_errata_sata24()
1972 switch (tf->command) { in mv_rw_multi_errata_sata24()
1974 tf->command = ATA_CMD_PIO_WRITE; in mv_rw_multi_errata_sata24()
1977 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ in mv_rw_multi_errata_sata24()
1980 tf->command = ATA_CMD_PIO_WRITE_EXT; in mv_rw_multi_errata_sata24()
1988 * mv_qc_prep - Host specific command preparation.
2001 struct ata_port *ap = qc->ap; in mv_qc_prep()
2002 struct mv_port_priv *pp = ap->private_data; in mv_qc_prep()
2004 struct ata_taskfile *tf = &qc->tf; in mv_qc_prep()
2008 switch (tf->protocol) { in mv_qc_prep()
2010 if (tf->command == ATA_CMD_DSM) in mv_qc_prep()
2024 if (!(tf->flags & ATA_TFLAG_WRITE)) in mv_qc_prep()
2026 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); in mv_qc_prep()
2027 flags |= qc->hw_tag << CRQB_TAG_SHIFT; in mv_qc_prep()
2028 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; in mv_qc_prep()
2031 in_index = pp->req_idx; in mv_qc_prep()
2033 pp->crqb[in_index].sg_addr = in mv_qc_prep()
2034 cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); in mv_qc_prep()
2035 pp->crqb[in_index].sg_addr_hi = in mv_qc_prep()
2036 cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); in mv_qc_prep()
2037 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); in mv_qc_prep()
2039 cw = &pp->crqb[in_index].ata_cmd[0]; in mv_qc_prep()
2041 /* Sadly, the CRQB cannot accommodate all registers--there are in mv_qc_prep()
2048 switch (tf->command) { in mv_qc_prep()
2054 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); in mv_qc_prep()
2058 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); in mv_qc_prep()
2059 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); in mv_qc_prep()
2062 /* The only other commands EDMA supports in non-queued and in mv_qc_prep()
2063 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none in mv_qc_prep()
2068 tf->command); in mv_qc_prep()
2071 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); in mv_qc_prep()
2072 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); in mv_qc_prep()
2073 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); in mv_qc_prep()
2074 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); in mv_qc_prep()
2075 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); in mv_qc_prep()
2076 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); in mv_qc_prep()
2077 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); in mv_qc_prep()
2078 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); in mv_qc_prep()
2079 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ in mv_qc_prep()
2081 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) in mv_qc_prep()
2089 * mv_qc_prep_iie - Host specific command preparation.
2102 struct ata_port *ap = qc->ap; in mv_qc_prep_iie()
2103 struct mv_port_priv *pp = ap->private_data; in mv_qc_prep_iie()
2105 struct ata_taskfile *tf = &qc->tf; in mv_qc_prep_iie()
2109 if ((tf->protocol != ATA_PROT_DMA) && in mv_qc_prep_iie()
2110 (tf->protocol != ATA_PROT_NCQ)) in mv_qc_prep_iie()
2112 if (tf->command == ATA_CMD_DSM) in mv_qc_prep_iie()
2116 if (!(tf->flags & ATA_TFLAG_WRITE)) in mv_qc_prep_iie()
2119 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); in mv_qc_prep_iie()
2120 flags |= qc->hw_tag << CRQB_TAG_SHIFT; in mv_qc_prep_iie()
2121 flags |= qc->hw_tag << CRQB_HOSTQ_SHIFT; in mv_qc_prep_iie()
2122 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; in mv_qc_prep_iie()
2125 in_index = pp->req_idx; in mv_qc_prep_iie()
2127 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; in mv_qc_prep_iie()
2128 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); in mv_qc_prep_iie()
2129 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); in mv_qc_prep_iie()
2130 crqb->flags = cpu_to_le32(flags); in mv_qc_prep_iie()
2132 crqb->ata_cmd[0] = cpu_to_le32( in mv_qc_prep_iie()
2133 (tf->command << 16) | in mv_qc_prep_iie()
2134 (tf->feature << 24) in mv_qc_prep_iie()
2136 crqb->ata_cmd[1] = cpu_to_le32( in mv_qc_prep_iie()
2137 (tf->lbal << 0) | in mv_qc_prep_iie()
2138 (tf->lbam << 8) | in mv_qc_prep_iie()
2139 (tf->lbah << 16) | in mv_qc_prep_iie()
2140 (tf->device << 24) in mv_qc_prep_iie()
2142 crqb->ata_cmd[2] = cpu_to_le32( in mv_qc_prep_iie()
2143 (tf->hob_lbal << 0) | in mv_qc_prep_iie()
2144 (tf->hob_lbam << 8) | in mv_qc_prep_iie()
2145 (tf->hob_lbah << 16) | in mv_qc_prep_iie()
2146 (tf->hob_feature << 24) in mv_qc_prep_iie()
2148 crqb->ata_cmd[3] = cpu_to_le32( in mv_qc_prep_iie()
2149 (tf->nsect << 0) | in mv_qc_prep_iie()
2150 (tf->hob_nsect << 8) in mv_qc_prep_iie()
2153 if (!(qc->flags & ATA_QCFLAG_DMAMAP)) in mv_qc_prep_iie()
2161 * mv_sff_check_status - fetch device status, if valid
2175 u8 stat = ioread8(ap->ioaddr.status_addr); in mv_sff_check_status()
2176 struct mv_port_priv *pp = ap->private_data; in mv_sff_check_status()
2178 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { in mv_sff_check_status()
2180 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; in mv_sff_check_status()
2188 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2191 * @nwords: number of 32-bit words in the fis
2197 int i, timeout = 200, final_word = nwords - 1; in mv_send_fis()
2208 /* Flag end-of-transmission, and then send the final word */ in mv_send_fis()
2218 } while (!(ifstat & 0x1000) && --timeout); in mv_send_fis()
2233 * mv_qc_issue_fis - Issue a command directly as a FIS
2243 * of non-data commands. So avoid sending them via this function,
2251 struct ata_port *ap = qc->ap; in mv_qc_issue_fis()
2252 struct mv_port_priv *pp = ap->private_data; in mv_qc_issue_fis()
2253 struct ata_link *link = qc->dev->link; in mv_qc_issue_fis()
2257 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); in mv_qc_issue_fis()
2262 switch (qc->tf.protocol) { in mv_qc_issue_fis()
2264 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; in mv_qc_issue_fis()
2267 ap->hsm_task_state = HSM_ST_FIRST; in mv_qc_issue_fis()
2270 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; in mv_qc_issue_fis()
2271 if (qc->tf.flags & ATA_TFLAG_WRITE) in mv_qc_issue_fis()
2272 ap->hsm_task_state = HSM_ST_FIRST; in mv_qc_issue_fis()
2274 ap->hsm_task_state = HSM_ST; in mv_qc_issue_fis()
2277 ap->hsm_task_state = HSM_ST_LAST; in mv_qc_issue_fis()
2281 if (qc->tf.flags & ATA_TFLAG_POLLING) in mv_qc_issue_fis()
2287 * mv_qc_issue - Initiate a command to the host
2301 struct ata_port *ap = qc->ap; in mv_qc_issue()
2303 struct mv_port_priv *pp = ap->private_data; in mv_qc_issue()
2307 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ in mv_qc_issue()
2309 switch (qc->tf.protocol) { in mv_qc_issue()
2311 if (qc->tf.command == ATA_CMD_DSM) { in mv_qc_issue()
2312 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */ in mv_qc_issue()
2318 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); in mv_qc_issue()
2319 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; in mv_qc_issue()
2320 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; in mv_qc_issue()
2323 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, in mv_qc_issue()
2339 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { in mv_qc_issue()
2340 --limit_warnings; in mv_qc_issue()
2341 ata_link_warn(qc->dev->link, DRV_NAME in mv_qc_issue()
2349 if (ap->flags & ATA_FLAG_PIO_POLLING) in mv_qc_issue()
2350 qc->tf.flags |= ATA_TFLAG_POLLING; in mv_qc_issue()
2354 if (qc->tf.flags & ATA_TFLAG_POLLING) in mv_qc_issue()
2360 * We're about to send a non-EDMA capable command to the in mv_qc_issue()
2366 mv_pmp_select(ap, qc->dev->link->pmp); in mv_qc_issue()
2368 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { in mv_qc_issue()
2369 struct mv_host_priv *hpriv = ap->host->private_data; in mv_qc_issue()
2374 * from libata-eh *must* use mv_qc_issue_fis(). in mv_qc_issue()
2377 * Rather than special-case it, we'll just *always* in mv_qc_issue()
2389 struct mv_port_priv *pp = ap->private_data; in mv_get_active_qc()
2392 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) in mv_get_active_qc()
2394 qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_get_active_qc()
2395 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) in mv_get_active_qc()
2403 struct mv_port_priv *pp = ap->private_data; in mv_pmp_error_handler()
2405 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { in mv_pmp_error_handler()
2412 pmp_map = pp->delayed_eh_pmp_map; in mv_pmp_error_handler()
2413 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; in mv_pmp_error_handler()
2417 struct ata_link *link = &ap->pmp_link[pmp]; in mv_pmp_error_handler()
2444 struct ata_link *link = &ap->pmp_link[pmp]; in mv_pmp_eh_prep()
2445 struct ata_eh_info *ehi = &link->eh_info; in mv_pmp_eh_prep()
2450 ehi->err_mask |= AC_ERR_DEV; in mv_pmp_eh_prep()
2451 ehi->action |= ATA_EH_RESET; in mv_pmp_eh_prep()
2471 struct mv_port_priv *pp = ap->private_data; in mv_handle_fbs_ncq_dev_err()
2480 * Perform the post-mortem/EH only when all responses are complete. in mv_handle_fbs_ncq_dev_err()
2483 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { in mv_handle_fbs_ncq_dev_err()
2484 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; in mv_handle_fbs_ncq_dev_err()
2485 pp->delayed_eh_pmp_map = 0; in mv_handle_fbs_ncq_dev_err()
2487 old_map = pp->delayed_eh_pmp_map; in mv_handle_fbs_ncq_dev_err()
2491 pp->delayed_eh_pmp_map = new_map; in mv_handle_fbs_ncq_dev_err()
2498 __func__, pp->delayed_eh_pmp_map, in mv_handle_fbs_ncq_dev_err()
2499 ap->qc_active, failed_links, in mv_handle_fbs_ncq_dev_err()
2500 ap->nr_active_links); in mv_handle_fbs_ncq_dev_err()
2502 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { in mv_handle_fbs_ncq_dev_err()
2518 * FBS+non-NCQ operation is not yet implemented. in mv_handle_fbs_non_ncq_dev_err()
2521 * Device error during FBS+non-NCQ operation: in mv_handle_fbs_non_ncq_dev_err()
2531 struct mv_port_priv *pp = ap->private_data; in mv_handle_dev_err()
2533 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) in mv_handle_dev_err()
2535 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) in mv_handle_dev_err()
2544 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { in mv_handle_dev_err()
2546 * EDMA should NOT have self-disabled for this case. in mv_handle_dev_err()
2552 __func__, edma_err_cause, pp->pp_flags); in mv_handle_dev_err()
2558 * EDMA should have self-disabled for this case. in mv_handle_dev_err()
2564 __func__, edma_err_cause, pp->pp_flags); in mv_handle_dev_err()
2574 struct ata_eh_info *ehi = &ap->link.eh_info; in mv_unexpected_intr()
2581 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_unexpected_intr()
2582 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) in mv_unexpected_intr()
2586 ehi->err_mask |= AC_ERR_OTHER; in mv_unexpected_intr()
2587 ehi->action |= ATA_EH_RESET; in mv_unexpected_intr()
2592 * mv_err_intr - Handle error interrupts on the port
2607 struct mv_port_priv *pp = ap->private_data; in mv_err_intr()
2608 struct mv_host_priv *hpriv = ap->host->private_data; in mv_err_intr()
2610 struct ata_eh_info *ehi = &ap->link.eh_info; in mv_err_intr()
2619 sata_scr_read(&ap->link, SCR_ERROR, &serr); in mv_err_intr()
2620 sata_scr_write_flush(&ap->link, SCR_ERROR, serr); in mv_err_intr()
2631 * Device errors during FIS-based switching operation in mv_err_intr()
2641 edma_err_cause, pp->pp_flags); in mv_err_intr()
2677 * Gen-I has a different SELF_DIS bit, in mv_err_intr()
2683 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_err_intr()
2684 ata_ehi_push_desc(ehi, "EDMA self-disable"); in mv_err_intr()
2689 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_err_intr()
2690 ata_ehi_push_desc(ehi, "EDMA self-disable"); in mv_err_intr()
2704 ehi->serror |= serr; in mv_err_intr()
2705 ehi->action |= action; in mv_err_intr()
2708 qc->err_mask |= err_mask; in mv_err_intr()
2710 ehi->err_mask |= err_mask; in mv_err_intr()
2731 ata_link_abort(qc->dev->link); in mv_err_intr()
2741 u16 edma_status = le16_to_cpu(response->flags); in mv_process_crpb_response()
2745 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). in mv_process_crpb_response()
2768 struct mv_host_priv *hpriv = ap->host->private_data; in mv_process_crpb_entries()
2772 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); in mv_process_crpb_entries()
2779 while (in_index != pp->resp_idx) { in mv_process_crpb_entries()
2781 struct mv_crpb *response = &pp->crpb[pp->resp_idx]; in mv_process_crpb_entries()
2783 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; in mv_process_crpb_entries()
2787 tag = ap->link.active_tag; in mv_process_crpb_entries()
2790 tag = le16_to_cpu(response->id) & 0x1f; in mv_process_crpb_entries()
2801 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | in mv_process_crpb_entries()
2802 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), in mv_process_crpb_entries()
2817 pp = ap->private_data; in mv_port_intr()
2818 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); in mv_port_intr()
2824 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) in mv_port_intr()
2828 * Handle chip-reported errors, or continue on to handle PIO. in mv_port_intr()
2842 * mv_host_intr - Handle all interrupts on the given host controller
2851 struct mv_host_priv *hpriv = host->private_data; in mv_host_intr()
2852 void __iomem *mmio = hpriv->base, *hc_mmio; in mv_host_intr()
2859 for (port = 0; port < hpriv->n_ports; port++) { in mv_host_intr()
2860 struct ata_port *ap = host->ports[port]; in mv_host_intr()
2875 port += MV_PORTS_PER_HC - 1; in mv_host_intr()
2894 if ((port + p) >= hpriv->n_ports) in mv_host_intr()
2916 struct mv_host_priv *hpriv = host->private_data; in mv_pci_error()
2923 err_cause = readl(mmio + hpriv->irq_cause_offset); in mv_pci_error()
2925 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause); in mv_pci_error()
2927 dev_dbg(host->dev, "%s: All regs @ PCI error\n", __func__); in mv_pci_error()
2928 mv_dump_all_regs(mmio, to_pci_dev(host->dev)); in mv_pci_error()
2930 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_pci_error()
2932 for (i = 0; i < host->n_ports; i++) { in mv_pci_error()
2933 ap = host->ports[i]; in mv_pci_error()
2934 if (!ata_link_offline(&ap->link)) { in mv_pci_error()
2935 ehi = &ap->link.eh_info; in mv_pci_error()
2941 ehi->action = ATA_EH_RESET; in mv_pci_error()
2942 qc = ata_qc_from_tag(ap, ap->link.active_tag); in mv_pci_error()
2944 qc->err_mask |= err_mask; in mv_pci_error()
2946 ehi->err_mask |= err_mask; in mv_pci_error()
2955 * mv_interrupt - Main interrupt event handler
2971 struct mv_host_priv *hpriv = host->private_data; in mv_interrupt()
2973 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; in mv_interrupt()
2976 spin_lock(&host->lock); in mv_interrupt()
2982 main_irq_cause = readl(hpriv->main_irq_cause_addr); in mv_interrupt()
2983 pending_irqs = main_irq_cause & hpriv->main_irq_mask; in mv_interrupt()
2990 handled = mv_pci_error(host, hpriv->base); in mv_interrupt()
2997 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); in mv_interrupt()
2999 spin_unlock(&host->lock); in mv_interrupt()
3023 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_read()
3024 void __iomem *mmio = hpriv->base; in mv5_scr_read()
3025 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); in mv5_scr_read()
3032 return -EINVAL; in mv5_scr_read()
3037 struct mv_host_priv *hpriv = link->ap->host->private_data; in mv5_scr_write()
3038 void __iomem *mmio = hpriv->base; in mv5_scr_write()
3039 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); in mv5_scr_write()
3046 return -EINVAL; in mv5_scr_write()
3051 struct pci_dev *pdev = to_pci_dev(host->dev); in mv5_reset_bus()
3054 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); in mv5_reset_bus()
3078 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ in mv5_read_preamp()
3079 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ in mv5_read_preamp()
3101 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); in mv5_phy_errata()
3116 tmp |= hpriv->signal[port].pre; in mv5_phy_errata()
3117 tmp |= hpriv->signal[port].amps; in mv5_phy_errata()
3169 struct mv_host_priv *hpriv = host->private_data; in mv5_reset_hc()
3187 struct mv_host_priv *hpriv = host->private_data; in mv_reset_pci_bus()
3198 ZERO(hpriv->irq_cause_offset); in mv_reset_pci_bus()
3199 ZERO(hpriv->irq_mask_offset); in mv_reset_pci_bus()
3220 * mv6_reset_hc - Perform the 6xxx global soft reset
3248 dev_err(host->dev, "PCI master won't flush\n"); in mv6_reset_hc()
3259 } while (!(GLOB_SFT_RST & t) && (i-- > 0)); in mv6_reset_hc()
3262 dev_err(host->dev, "can't set global reset\n"); in mv6_reset_hc()
3273 } while ((GLOB_SFT_RST & t) && (i-- > 0)); in mv6_reset_hc()
3276 dev_err(host->dev, "can't clear global reset\n"); in mv6_reset_hc()
3291 hpriv->signal[idx].amps = 0x7 << 8; in mv6_read_preamp()
3292 hpriv->signal[idx].pre = 0x1 << 5; in mv6_read_preamp()
3299 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv6_read_preamp()
3300 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv6_read_preamp()
3313 u32 hp_flags = hpriv->hp_flags; in mv6_phy_errata()
3336 * Gen-II/IIe PHY_MODE3 errata RM#2: in mv6_phy_errata()
3342 /* Guideline 88F5182 (GL# SATA-S11) */ in mv6_phy_errata()
3349 * Enforce reserved-bit restrictions on GenIIe devices only. in mv6_phy_errata()
3360 * Workaround for 60x1-B2 errata SATA#13: in mv6_phy_errata()
3367 /* Revert values of pre-emphasis and signal amps to the saved ones */ in mv6_phy_errata()
3371 m2 |= hpriv->signal[port].amps; in mv6_phy_errata()
3372 m2 |= hpriv->signal[port].pre; in mv6_phy_errata()
3401 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ in mv_soc_read_preamp()
3402 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ in mv_soc_read_preamp()
3448 struct mv_host_priv *hpriv = host->private_data; in mv_soc_reset_hc()
3451 for (port = 0; port < hpriv->n_ports; port++) in mv_soc_reset_hc()
3502 * soc_is_65 - check if the soc is 65 nano device
3505 * register, this register should contain non-zero value and it exists only
3510 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); in soc_is_65n()
3553 hpriv->ops->phy_errata(hpriv, mmio, port_no); in mv_reset_channel()
3576 mv_pmp_select(link->ap, sata_srst_pmp(link)); in mv_pmp_hardreset()
3583 mv_pmp_select(link->ap, sata_srst_pmp(link)); in mv_softreset()
3590 struct ata_port *ap = link->ap; in mv_hardreset()
3591 struct mv_host_priv *hpriv = ap->host->private_data; in mv_hardreset()
3592 struct mv_port_priv *pp = ap->private_data; in mv_hardreset()
3593 void __iomem *mmio = hpriv->base; in mv_hardreset()
3598 mv_reset_channel(hpriv, mmio, ap->port_no); in mv_hardreset()
3599 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; in mv_hardreset()
3600 pp->pp_flags &= in mv_hardreset()
3606 sata_ehc_deb_timing(&link->eh_context); in mv_hardreset()
3610 rc = online ? -EAGAIN : rc; in mv_hardreset()
3618 extra = HZ; /* only extend it once, max */ in mv_hardreset()
3635 struct mv_host_priv *hpriv = ap->host->private_data; in mv_eh_thaw()
3636 unsigned int port = ap->port_no; in mv_eh_thaw()
3638 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); in mv_eh_thaw()
3653 * mv_port_init - Perform some early initialization on a single port.
3670 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); in mv_port_init()
3671 port->error_addr = in mv_port_init()
3672 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); in mv_port_init()
3673 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); in mv_port_init()
3674 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); in mv_port_init()
3675 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); in mv_port_init()
3676 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); in mv_port_init()
3677 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); in mv_port_init()
3678 port->status_addr = in mv_port_init()
3679 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); in mv_port_init()
3681 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; in mv_port_init()
3688 /* unmask all non-transient EDMA error interrupts */ in mv_port_init()
3694 struct mv_host_priv *hpriv = host->private_data; in mv_in_pcix_mode()
3695 void __iomem *mmio = hpriv->base; in mv_in_pcix_mode()
3699 return 0; /* not PCI-X capable */ in mv_in_pcix_mode()
3703 return 1; /* chip is in PCI-X mode */ in mv_in_pcix_mode()
3708 struct mv_host_priv *hpriv = host->private_data; in mv_pci_cut_through_okay()
3709 void __iomem *mmio = hpriv->base; in mv_pci_cut_through_okay()
3722 struct mv_host_priv *hpriv = host->private_data; in mv_60x1b2_errata_pci7()
3723 void __iomem *mmio = hpriv->base; in mv_60x1b2_errata_pci7()
3725 /* workaround for 60x1-B2 errata PCI#7 */ in mv_60x1b2_errata_pci7()
3734 struct pci_dev *pdev = to_pci_dev(host->dev); in mv_chip_id()
3735 struct mv_host_priv *hpriv = host->private_data; in mv_chip_id()
3736 u32 hp_flags = hpriv->hp_flags; in mv_chip_id()
3740 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3743 switch (pdev->revision) { in mv_chip_id()
3751 dev_warn(&pdev->dev, in mv_chip_id()
3760 hpriv->ops = &mv5xxx_ops; in mv_chip_id()
3763 switch (pdev->revision) { in mv_chip_id()
3771 dev_warn(&pdev->dev, in mv_chip_id()
3780 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3783 switch (pdev->revision) { in mv_chip_id()
3792 dev_warn(&pdev->dev, in mv_chip_id()
3801 if (pdev->vendor == PCI_VENDOR_ID_TTI && in mv_chip_id()
3802 (pdev->device == 0x2300 || pdev->device == 0x2310)) in mv_chip_id()
3817 * RAID metadata is at: (dev->n_sectors & ~0xfffff) in mv_chip_id()
3821 dev_warn(&pdev->dev, "Highpoint RocketRAID" in mv_chip_id()
3825 dev_warn(&pdev->dev, "For data safety, do not" in mv_chip_id()
3826 " use sectors 8-9 on \"Legacy\" drives," in mv_chip_id()
3832 hpriv->ops = &mv6xxx_ops; in mv_chip_id()
3837 switch (pdev->revision) { in mv_chip_id()
3842 dev_warn(&pdev->dev, in mv_chip_id()
3850 hpriv->ops = &mv_soc_65n_ops; in mv_chip_id()
3852 hpriv->ops = &mv_soc_ops; in mv_chip_id()
3858 dev_alert(host->dev, "BUG: invalid board index %u\n", board_idx); in mv_chip_id()
3859 return -EINVAL; in mv_chip_id()
3862 hpriv->hp_flags = hp_flags; in mv_chip_id()
3864 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; in mv_chip_id()
3865 hpriv->irq_mask_offset = PCIE_IRQ_MASK; in mv_chip_id()
3866 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; in mv_chip_id()
3868 hpriv->irq_cause_offset = PCI_IRQ_CAUSE; in mv_chip_id()
3869 hpriv->irq_mask_offset = PCI_IRQ_MASK; in mv_chip_id()
3870 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; in mv_chip_id()
3877 * mv_init_host - Perform some early initialization of the host.
3889 struct mv_host_priv *hpriv = host->private_data; in mv_init_host()
3890 void __iomem *mmio = hpriv->base; in mv_init_host()
3892 rc = mv_chip_id(host, hpriv->board_idx); in mv_init_host()
3897 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3898 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; in mv_init_host()
3900 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; in mv_init_host()
3901 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; in mv_init_host()
3905 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); in mv_init_host()
3910 n_hc = mv_get_hc_count(host->ports[0]->flags); in mv_init_host()
3912 for (port = 0; port < host->n_ports; port++) in mv_init_host()
3913 if (hpriv->ops->read_preamp) in mv_init_host()
3914 hpriv->ops->read_preamp(hpriv, port, mmio); in mv_init_host()
3916 rc = hpriv->ops->reset_hc(host, mmio, n_hc); in mv_init_host()
3920 hpriv->ops->reset_flash(hpriv, mmio); in mv_init_host()
3921 hpriv->ops->reset_bus(host, mmio); in mv_init_host()
3922 hpriv->ops->enable_leds(hpriv, mmio); in mv_init_host()
3924 for (port = 0; port < host->n_ports; port++) { in mv_init_host()
3925 struct ata_port *ap = host->ports[port]; in mv_init_host()
3928 mv_port_init(&ap->ioaddr, port_mmio); in mv_init_host()
3934 dev_dbg(host->dev, "HC%i: HC config=0x%08x HC IRQ cause " in mv_init_host()
3945 writelfl(0, mmio + hpriv->irq_cause_offset); in mv_init_host()
3948 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); in mv_init_host()
3953 * The per-port interrupts get done later as ports are set up. in mv_init_host()
3964 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, in mv_create_dma_pools()
3966 if (!hpriv->crqb_pool) in mv_create_dma_pools()
3967 return -ENOMEM; in mv_create_dma_pools()
3969 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, in mv_create_dma_pools()
3971 if (!hpriv->crpb_pool) in mv_create_dma_pools()
3972 return -ENOMEM; in mv_create_dma_pools()
3974 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, in mv_create_dma_pools()
3976 if (!hpriv->sg_tbl_pool) in mv_create_dma_pools()
3977 return -ENOMEM; in mv_create_dma_pools()
3988 writel(0, hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
3989 writel(0, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
3992 for (i = 0; i < dram->num_cs; i++) { in mv_conf_mbus_windows()
3993 const struct mbus_dram_window *cs = dram->cs + i; in mv_conf_mbus_windows()
3995 writel(((cs->size - 1) & 0xffff0000) | in mv_conf_mbus_windows()
3996 (cs->mbus_attr << 8) | in mv_conf_mbus_windows()
3997 (dram->mbus_dram_target_id << 4) | 1, in mv_conf_mbus_windows()
3998 hpriv->base + WINDOW_CTRL(i)); in mv_conf_mbus_windows()
3999 writel(cs->base, hpriv->base + WINDOW_BASE(i)); in mv_conf_mbus_windows()
4004 * mv_platform_probe - handle a positive probe of an soc Marvell
4024 ata_print_version_once(&pdev->dev, DRV_VERSION); in mv_platform_probe()
4029 if (unlikely(pdev->num_resources != 1)) { in mv_platform_probe()
4030 dev_err(&pdev->dev, "invalid number of resources\n"); in mv_platform_probe()
4031 return -EINVAL; in mv_platform_probe()
4039 return -EINVAL; in mv_platform_probe()
4042 if (pdev->dev.of_node) { in mv_platform_probe()
4043 rc = of_property_read_u32(pdev->dev.of_node, "nr-ports", in mv_platform_probe()
4046 dev_err(&pdev->dev, in mv_platform_probe()
4047 "error parsing nr-ports property: %d\n", rc); in mv_platform_probe()
4052 dev_err(&pdev->dev, "nr-ports must be positive: %d\n", in mv_platform_probe()
4054 return -EINVAL; in mv_platform_probe()
4057 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); in mv_platform_probe()
4059 mv_platform_data = dev_get_platdata(&pdev->dev); in mv_platform_probe()
4060 n_ports = mv_platform_data->n_ports; in mv_platform_probe()
4066 return -EINVAL; in mv_platform_probe()
4068 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); in mv_platform_probe()
4069 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_platform_probe()
4072 return -ENOMEM; in mv_platform_probe()
4073 hpriv->port_clks = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4076 if (!hpriv->port_clks) in mv_platform_probe()
4077 return -ENOMEM; in mv_platform_probe()
4078 hpriv->port_phys = devm_kcalloc(&pdev->dev, in mv_platform_probe()
4081 if (!hpriv->port_phys) in mv_platform_probe()
4082 return -ENOMEM; in mv_platform_probe()
4083 host->private_data = hpriv; in mv_platform_probe()
4084 hpriv->board_idx = chip_soc; in mv_platform_probe()
4086 host->iomap = NULL; in mv_platform_probe()
4087 hpriv->base = devm_ioremap(&pdev->dev, res->start, in mv_platform_probe()
4089 if (!hpriv->base) in mv_platform_probe()
4090 return -ENOMEM; in mv_platform_probe()
4092 hpriv->base -= SATAHC0_REG_BASE; in mv_platform_probe()
4094 hpriv->clk = clk_get(&pdev->dev, NULL); in mv_platform_probe()
4095 if (IS_ERR(hpriv->clk)) { in mv_platform_probe()
4096 dev_notice(&pdev->dev, "cannot get optional clkdev\n"); in mv_platform_probe()
4098 rc = clk_prepare_enable(hpriv->clk); in mv_platform_probe()
4106 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number); in mv_platform_probe()
4107 if (!IS_ERR(hpriv->port_clks[port])) in mv_platform_probe()
4108 clk_prepare_enable(hpriv->port_clks[port]); in mv_platform_probe()
4111 hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev, in mv_platform_probe()
4113 if (IS_ERR(hpriv->port_phys[port])) { in mv_platform_probe()
4114 rc = PTR_ERR(hpriv->port_phys[port]); in mv_platform_probe()
4115 hpriv->port_phys[port] = NULL; in mv_platform_probe()
4116 if (rc != -EPROBE_DEFER) in mv_platform_probe()
4117 dev_warn(&pdev->dev, "error getting phy %d", rc); in mv_platform_probe()
4120 hpriv->n_ports = port; in mv_platform_probe()
4123 phy_power_on(hpriv->port_phys[port]); in mv_platform_probe()
4127 hpriv->n_ports = n_ports; in mv_platform_probe()
4130 * (Re-)program MBUS remapping windows if we are asked to. in mv_platform_probe()
4136 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_platform_probe()
4144 if (pdev->dev.of_node && in mv_platform_probe()
4145 of_device_is_compatible(pdev->dev.of_node, in mv_platform_probe()
4146 "marvell,armada-370-sata")) in mv_platform_probe()
4147 hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL; in mv_platform_probe()
4154 dev_info(&pdev->dev, "slots %u ports %d\n", in mv_platform_probe()
4155 (unsigned)MV_MAX_Q_DEPTH, host->n_ports); in mv_platform_probe()
4162 if (!IS_ERR(hpriv->clk)) { in mv_platform_probe()
4163 clk_disable_unprepare(hpriv->clk); in mv_platform_probe()
4164 clk_put(hpriv->clk); in mv_platform_probe()
4166 for (port = 0; port < hpriv->n_ports; port++) { in mv_platform_probe()
4167 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_probe()
4168 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_probe()
4169 clk_put(hpriv->port_clks[port]); in mv_platform_probe()
4171 phy_power_off(hpriv->port_phys[port]); in mv_platform_probe()
4179 * mv_platform_remove - unplug a platform interface
4188 struct mv_host_priv *hpriv = host->private_data; in mv_platform_remove()
4192 if (!IS_ERR(hpriv->clk)) { in mv_platform_remove()
4193 clk_disable_unprepare(hpriv->clk); in mv_platform_remove()
4194 clk_put(hpriv->clk); in mv_platform_remove()
4196 for (port = 0; port < host->n_ports; port++) { in mv_platform_remove()
4197 if (!IS_ERR(hpriv->port_clks[port])) { in mv_platform_remove()
4198 clk_disable_unprepare(hpriv->port_clks[port]); in mv_platform_remove()
4199 clk_put(hpriv->port_clks[port]); in mv_platform_remove()
4201 phy_power_off(hpriv->port_phys[port]); in mv_platform_remove()
4222 struct mv_host_priv *hpriv = host->private_data; in mv_platform_resume()
4225 * (Re-)program MBUS remapping windows if we are asked to. in mv_platform_resume()
4234 dev_err(&pdev->dev, "Error during HW init\n"); in mv_platform_resume()
4249 { .compatible = "marvell,armada-370-sata", },
4250 { .compatible = "marvell,orion-sata", },
4320 * mv_print_info - Dump key info to kernel log for perusal.
4330 struct pci_dev *pdev = to_pci_dev(host->dev); in mv_print_info()
4331 struct mv_host_priv *hpriv = host->private_data; in mv_print_info()
4355 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n", in mv_print_info()
4356 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, in mv_print_info()
4357 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); in mv_print_info()
4361 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
4371 unsigned int board_idx = (unsigned int)ent->driver_data; in mv_pci_init_one()
4377 ata_print_version_once(&pdev->dev, DRV_VERSION); in mv_pci_init_one()
4380 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; in mv_pci_init_one()
4382 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); in mv_pci_init_one()
4383 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); in mv_pci_init_one()
4385 return -ENOMEM; in mv_pci_init_one()
4386 host->private_data = hpriv; in mv_pci_init_one()
4387 hpriv->n_ports = n_ports; in mv_pci_init_one()
4388 hpriv->board_idx = board_idx; in mv_pci_init_one()
4396 if (rc == -EBUSY) in mv_pci_init_one()
4400 host->iomap = pcim_iomap_table(pdev); in mv_pci_init_one()
4401 hpriv->base = host->iomap[MV_PRIMARY_BAR]; in mv_pci_init_one()
4403 rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in mv_pci_init_one()
4405 dev_err(&pdev->dev, "DMA enable failed\n"); in mv_pci_init_one()
4409 rc = mv_create_dma_pools(hpriv, &pdev->dev); in mv_pci_init_one()
4413 for (port = 0; port < host->n_ports; port++) { in mv_pci_init_one()
4414 struct ata_port *ap = host->ports[port]; in mv_pci_init_one()
4415 void __iomem *port_mmio = mv_port_base(hpriv->base, port); in mv_pci_init_one()
4416 unsigned int offset = port_mmio - hpriv->base; in mv_pci_init_one()
4418 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); in mv_pci_init_one()
4427 /* Enable message-switched interrupts, if requested */ in mv_pci_init_one()
4429 hpriv->hp_flags |= MV_HP_FLAG_MSI; in mv_pci_init_one()
4436 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, in mv_pci_init_one()
4464 int rc = -ENODEV; in mv_init()
4488 MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");