Lines Matching +full:master +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
24 * struct ftide010 - state container for the Faraday FTIDE010
29 * @master_cbl: master cable type
32 * @master_to_sata0: Gemini SATA bridge: the ATA master is connected
36 * @master_to_sata1: Gemini SATA bridge: the ATA master is connected
48 /* Gemini-specific properties */
62 #define FTIDE010_UDMA_TIMING0 0x12 /* Master */
76 /* Set this bit for UDMA mode 5 and 6 */
98 * pio_active_time: array of 5 elements for T2 timing for Mode 0,
100 * pio_recovery_time: array of 5 elements for T2l timing for Mode 0,
103 * word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15.
105 * multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15.
107 * word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
109 * multi word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
111 * DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz. Range 0..7.
113 * multi word DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz, Range 0..7.
115 * word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
117 * multi word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
142 struct ftide010 *ftide = ap->host->private_data; in ftide010_set_dmamode()
143 u8 speed = adev->dma_mode; in ftide010_set_dmamode()
144 u8 devno = adev->devno & 1; in ftide010_set_dmamode()
151 /* Target device 0 (master) or 1 (slave) */ in ftide010_set_dmamode()
160 clkreg = readb(ftide->base + FTIDE010_CLK_MOD); in ftide010_set_dmamode()
166 dev_dbg(ftide->dev, "set UDMA mode %02x, index %d\n", in ftide010_set_dmamode()
183 dev_dbg(ftide->dev, "UDMA write clkreg = %02x, timreg = %02x\n", in ftide010_set_dmamode()
186 writeb(clkreg, ftide->base + FTIDE010_CLK_MOD); in ftide010_set_dmamode()
187 writeb(timreg, ftide->base + FTIDE010_UDMA_TIMING0 + devno); in ftide010_set_dmamode()
190 dev_dbg(ftide->dev, "set MWDMA mode %02x, index %d\n", in ftide010_set_dmamode()
201 dev_dbg(ftide->dev, in ftide010_set_dmamode()
205 writeb(clkreg, ftide->base + FTIDE010_CLK_MOD); in ftide010_set_dmamode()
206 writeb(timreg, ftide->base + FTIDE010_MWDMA_TIMING); in ftide010_set_dmamode()
210 * Store the current device (master or slave) in ap->private_data in ftide010_set_dmamode()
214 ap->private_data = adev; in ftide010_set_dmamode()
221 struct ftide010 *ftide = ap->host->private_data; in ftide010_set_piomode()
222 u8 pio = adev->pio_mode - XFER_PIO_0; in ftide010_set_piomode()
224 dev_dbg(ftide->dev, "set PIO mode %02x, index %d\n", in ftide010_set_piomode()
225 adev->pio_mode, pio); in ftide010_set_piomode()
227 ftide->base + FTIDE010_PIO_TIMING); in ftide010_set_piomode()
232 * the timings differently for master and slave transfers: the CLK_MOD_REG
233 * and MWDMA_TIMING_REG is shared between master and slave, so reprogramming
238 struct ata_port *ap = qc->ap; in ftide010_qc_issue()
239 struct ata_device *adev = qc->dev; in ftide010_qc_issue()
242 * If the device changed, i.e. slave->master, master->slave, in ftide010_qc_issue()
243 * then set up the DMA mode again so we are sure the timings in ftide010_qc_issue()
246 if (adev != ap->private_data && ata_dma_enabled(adev)) in ftide010_qc_issue()
271 struct ftide010 *ftide = ap->host->private_data; in pata_ftide010_gemini_port_start()
272 struct device *dev = ftide->dev; in pata_ftide010_gemini_port_start()
273 struct sata_gemini *sg = ftide->sg; in pata_ftide010_gemini_port_start()
281 if (ftide->master_to_sata0) { in pata_ftide010_gemini_port_start()
282 dev_info(dev, "SATA0 (master) start\n"); in pata_ftide010_gemini_port_start()
287 if (ftide->master_to_sata1) { in pata_ftide010_gemini_port_start()
288 dev_info(dev, "SATA1 (master) start\n"); in pata_ftide010_gemini_port_start()
293 /* Avoid double-starting */ in pata_ftide010_gemini_port_start()
294 if (ftide->slave_to_sata0 && !ftide->master_to_sata0) { in pata_ftide010_gemini_port_start()
300 /* Avoid double-starting */ in pata_ftide010_gemini_port_start()
301 if (ftide->slave_to_sata1 && !ftide->master_to_sata1) { in pata_ftide010_gemini_port_start()
309 return (bridges > 0) ? 0 : -EINVAL; // -ENODEV; in pata_ftide010_gemini_port_start()
314 struct ftide010 *ftide = ap->host->private_data; in pata_ftide010_gemini_port_stop()
315 struct device *dev = ftide->dev; in pata_ftide010_gemini_port_stop()
316 struct sata_gemini *sg = ftide->sg; in pata_ftide010_gemini_port_stop()
318 if (ftide->master_to_sata0) { in pata_ftide010_gemini_port_stop()
319 dev_info(dev, "SATA0 (master) stop\n"); in pata_ftide010_gemini_port_stop()
322 if (ftide->master_to_sata1) { in pata_ftide010_gemini_port_stop()
323 dev_info(dev, "SATA1 (master) stop\n"); in pata_ftide010_gemini_port_stop()
326 /* Avoid double-stopping */ in pata_ftide010_gemini_port_stop()
327 if (ftide->slave_to_sata0 && !ftide->master_to_sata0) { in pata_ftide010_gemini_port_stop()
331 /* Avoid double-stopping */ in pata_ftide010_gemini_port_stop()
332 if (ftide->slave_to_sata1 && !ftide->master_to_sata1) { in pata_ftide010_gemini_port_stop()
340 struct ftide010 *ftide = ap->host->private_data; in pata_ftide010_gemini_cable_detect()
343 * Return the master cable, I have no clue how to return a different in pata_ftide010_gemini_cable_detect()
344 * cable for the slave than for the master. in pata_ftide010_gemini_cable_detect()
346 return ftide->master_cbl; in pata_ftide010_gemini_cable_detect()
353 struct device *dev = ftide->dev; in pata_ftide010_gemini_init()
361 ftide->sg = sg; in pata_ftide010_gemini_init()
373 /* Flag port as SATA-capable */ in pata_ftide010_gemini_init()
375 pi->flags |= ATA_FLAG_SATA; in pata_ftide010_gemini_init()
379 pi->mwdma_mask = 0; in pata_ftide010_gemini_init()
380 pi->udma_mask = 0; in pata_ftide010_gemini_init()
384 * We assume that a simple 40-wire cable is used in the PATA mode. in pata_ftide010_gemini_init()
393 ftide->master_cbl = ATA_CBL_SATA; in pata_ftide010_gemini_init()
394 ftide->slave_cbl = ATA_CBL_PATA40; in pata_ftide010_gemini_init()
395 ftide->master_to_sata0 = true; in pata_ftide010_gemini_init()
398 ftide->master_cbl = ATA_CBL_SATA; in pata_ftide010_gemini_init()
399 ftide->slave_cbl = ATA_CBL_NONE; in pata_ftide010_gemini_init()
400 ftide->master_to_sata0 = true; in pata_ftide010_gemini_init()
403 ftide->master_cbl = ATA_CBL_PATA40; in pata_ftide010_gemini_init()
404 ftide->slave_cbl = ATA_CBL_PATA40; in pata_ftide010_gemini_init()
407 ftide->master_cbl = ATA_CBL_SATA; in pata_ftide010_gemini_init()
408 ftide->slave_cbl = ATA_CBL_SATA; in pata_ftide010_gemini_init()
409 ftide->master_to_sata0 = true; in pata_ftide010_gemini_init()
410 ftide->slave_to_sata1 = true; in pata_ftide010_gemini_init()
416 ftide->master_cbl = ATA_CBL_SATA; in pata_ftide010_gemini_init()
417 ftide->slave_cbl = ATA_CBL_NONE; in pata_ftide010_gemini_init()
418 ftide->master_to_sata1 = true; in pata_ftide010_gemini_init()
421 ftide->master_cbl = ATA_CBL_SATA; in pata_ftide010_gemini_init()
422 ftide->slave_cbl = ATA_CBL_PATA40; in pata_ftide010_gemini_init()
423 ftide->master_to_sata1 = true; in pata_ftide010_gemini_init()
426 ftide->master_cbl = ATA_CBL_SATA; in pata_ftide010_gemini_init()
427 ftide->slave_cbl = ATA_CBL_SATA; in pata_ftide010_gemini_init()
428 ftide->slave_to_sata0 = true; in pata_ftide010_gemini_init()
429 ftide->master_to_sata1 = true; in pata_ftide010_gemini_init()
432 ftide->master_cbl = ATA_CBL_PATA40; in pata_ftide010_gemini_init()
433 ftide->slave_cbl = ATA_CBL_PATA40; in pata_ftide010_gemini_init()
446 return -ENOTSUPP; in pata_ftide010_gemini_init()
453 struct device *dev = &pdev->dev; in pata_ftide010_probe()
454 struct device_node *np = dev->of_node; in pata_ftide010_probe()
465 return -ENOMEM; in pata_ftide010_probe()
466 ftide->dev = dev; in pata_ftide010_probe()
472 ftide->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in pata_ftide010_probe()
473 if (IS_ERR(ftide->base)) in pata_ftide010_probe()
474 return PTR_ERR(ftide->base); in pata_ftide010_probe()
476 ftide->pclk = devm_clk_get(dev, "PCLK"); in pata_ftide010_probe()
477 if (!IS_ERR(ftide->pclk)) { in pata_ftide010_probe()
478 ret = clk_prepare_enable(ftide->pclk); in pata_ftide010_probe()
486 if (of_device_is_compatible(np, "cortina,gemini-pata")) { in pata_ftide010_probe()
496 (res->start == 0x63400000)); in pata_ftide010_probe()
501 ftide->master_cbl = ATA_CBL_PATA40; in pata_ftide010_probe()
502 ftide->slave_cbl = ATA_CBL_PATA40; in pata_ftide010_probe()
505 ftide->host = ata_host_alloc_pinfo(dev, ppi, 1); in pata_ftide010_probe()
506 if (!ftide->host) { in pata_ftide010_probe()
507 ret = -ENOMEM; in pata_ftide010_probe()
510 ftide->host->private_data = ftide; in pata_ftide010_probe()
512 for (i = 0; i < ftide->host->n_ports; i++) { in pata_ftide010_probe()
513 struct ata_port *ap = ftide->host->ports[i]; in pata_ftide010_probe()
514 struct ata_ioports *ioaddr = &ap->ioaddr; in pata_ftide010_probe()
516 ioaddr->bmdma_addr = ftide->base + FTIDE010_DMA_REG; in pata_ftide010_probe()
517 ioaddr->cmd_addr = ftide->base + FTIDE010_CMD_DATA; in pata_ftide010_probe()
518 ioaddr->ctl_addr = ftide->base + FTIDE010_ALTSTAT_CTRL; in pata_ftide010_probe()
519 ioaddr->altstatus_addr = ftide->base + FTIDE010_ALTSTAT_CTRL; in pata_ftide010_probe()
524 readl(ftide->base + FTIDE010_IDE_DEVICE_ID), irq, res); in pata_ftide010_probe()
526 ret = ata_host_activate(ftide->host, irq, ata_bmdma_interrupt, in pata_ftide010_probe()
534 clk_disable_unprepare(ftide->pclk); in pata_ftide010_probe()
542 struct ftide010 *ftide = host->private_data; in pata_ftide010_remove()
544 ata_host_detach(ftide->host); in pata_ftide010_remove()
545 clk_disable_unprepare(ftide->pclk); in pata_ftide010_remove()