Lines Matching +full:5 +full:mhz

76 /* Set this bit for UDMA mode 5 and 6 */
79 /* 0 = 50 MHz, 1 = 66 MHz */
84 #define FTIDE010_CLK_MOD_DEV1_UDMA_EN	BIT(5)
94  * reference clock which is 30 nanoseconds per unit at 66MHz and 20
95  * nanoseconds per unit at 50 MHz. The PIO timings assume 33MHz speed for
98  * pio_active_time: array of 5 elements for T2 timing for Mode 0,
100  * pio_recovery_time: array of 5 elements for T2l timing for Mode 0,
103  * word DMA, Mode 0, 1, and 2 at 50 MHz. Range 0..15.
105  * multi word DMA, Mode 0, 1 and 2 at 50 MHz. Range 0..15.
107  * word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
109  * multi word DMA, Mode 0, 1 and 2 at 66 MHz. Range 0..15.
111  * DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz. Range 0..7.
113  * multi word DMA, Mode 0, 1, 2, 3, 4 and 5 at 50 MHz, Range 0..7.
115  * word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
117  * multi word DMA, Mode 0, 1, 2, 3, 4, 5 and 6 at 66 MHz. Range 0..7.
119 static const u8 pio_active_time[5] = {10, 10, 10, 3, 3};
120 static const u8 pio_recovery_time[5] = {10, 3, 1, 3, 1};
131  * We set 66 MHz for all MWDMA modes
136  * We set 66 MHz for UDMA modes 3, 4 and 6 and no others
179 		/* A special bit needs to be set for modes 5 and 6 */  in ftide010_set_dmamode()
180 		if (i >= 5)  in ftide010_set_dmamode()