Lines Matching defs:val
21 #define REGB_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regb, (reg), (val), #reg, __func__)
22 #define REGB_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regb, (reg), (val), #reg, __func__)
26 #define REGV_WR32(reg, val) ivpu_hw_reg_wr32(vdev, vdev->regv, (reg), (val), #reg, __func__)
27 #define REGV_WR64(reg, val) ivpu_hw_reg_wr64(vdev, vdev->regv, (reg), (val), #reg, __func__)
29 #define REGV_WR32I(reg, stride, index, val) \
30 ivpu_hw_reg_wr32_index(vdev, vdev->regv, (reg), (stride), (index), (val), #reg, __func__)
36 #define REG_GET_FLD(REG, FLD, val) \
37 FIELD_GET(REG##_##FLD##_MASK, val)
38 #define REG_CLR_FLD(REG, FLD, val) \
39 ((val) & ~(REG##_##FLD##_MASK))
40 #define REG_SET_FLD(REG, FLD, val) \
41 ((val) | (REG##_##FLD##_MASK))
42 #define REG_SET_FLD_NUM(REG, FLD, num, val) \
43 (((val) & ~(REG##_##FLD##_MASK)) | FIELD_PREP(REG##_##FLD##_MASK, num))
44 #define REG_TEST_FLD(REG, FLD, val) \
45 ((REG##_##FLD##_MASK) == ((val) & (REG##_##FLD##_MASK)))
46 #define REG_TEST_FLD_NUM(REG, FLD, num, val) \
47 ((num) == FIELD_GET(REG##_##FLD##_MASK, val))
90 u32 val = readl(base + reg);
92 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%08x\n", func, name, reg, val);
93 return val;
100 u64 val = readq(base + reg);
102 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) RD: 0x%016llx\n", func, name, reg, val);
103 return val;
107 ivpu_hw_reg_wr32(struct ivpu_device *vdev, void __iomem *base, u32 reg, u32 val,
110 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%08x\n", func, name, reg, val);
111 writel(val, base + reg);
115 ivpu_hw_reg_wr64(struct ivpu_device *vdev, void __iomem *base, u32 reg, u64 val,
118 ivpu_dbg(vdev, REG, "%s : %s (0x%08x) WR: 0x%016llx\n", func, name, reg, val);
119 writeq(val, base + reg);
124 u32 stride, u32 index, u32 val, const char *name,
129 ivpu_dbg(vdev, REG, "%s WR: %s_%d (0x%08x) <= 0x%08x\n", func, name, index, reg, val);
130 writel(val, base + reg);