5015 				u32 queue_id_base)  in gaudi2_init_qman_pq()  argument
5021 		q = &hdev->kernel_queues[queue_id_base + pq_id];  in gaudi2_init_qman_pq()
5064 				u32 queue_id_base)  in gaudi2_init_qman_pqc()  argument
5093 static u32 gaudi2_get_dyn_sp_reg(struct hl_device *hdev, u32 queue_id_base)  in gaudi2_get_dyn_sp_reg()  argument
5098 	switch (queue_id_base) {  in gaudi2_get_dyn_sp_reg()
5135 		dev_err(hdev->dev, "Unexpected h/w queue %d\n", queue_id_base);  in gaudi2_get_dyn_sp_reg()
5143 					u32 queue_id_base)  in gaudi2_init_qman_common()  argument
5150 	irq_handler_offset = gaudi2_get_dyn_sp_reg(hdev, queue_id_base);  in gaudi2_init_qman_common()
5154 	map_table_entry = gaudi2_qman_async_event_id[queue_id_base];  in gaudi2_init_qman_common()
5179 		u32 queue_id_base)  in gaudi2_init_qman()  argument
5184 		hdev->kernel_queues[queue_id_base + pq_id].cq_id = GAUDI2_RESERVED_CQ_CS_COMPLETION;  in gaudi2_init_qman()
5186 	gaudi2_init_qman_pq(hdev, reg_base, queue_id_base);  in gaudi2_init_qman()
5188 	gaudi2_init_qman_pqc(hdev, reg_base, queue_id_base);  in gaudi2_init_qman()
5189 	gaudi2_init_qman_common(hdev, reg_base, queue_id_base);  in gaudi2_init_qman()
5468 	u32 queue_id_base, reg_base;  in gaudi2_init_dcore_mme()  local
5472 		queue_id_base = GAUDI2_QUEUE_ID_DCORE0_MME_0_0;  in gaudi2_init_dcore_mme()
5475 		queue_id_base = GAUDI2_QUEUE_ID_DCORE1_MME_0_0;  in gaudi2_init_dcore_mme()
5478 		queue_id_base = GAUDI2_QUEUE_ID_DCORE2_MME_0_0;  in gaudi2_init_dcore_mme()
5481 		queue_id_base = GAUDI2_QUEUE_ID_DCORE3_MME_0_0;  in gaudi2_init_dcore_mme()
5493 	reg_base = gaudi2_qm_blocks_bases[queue_id_base];  in gaudi2_init_dcore_mme()
5494 	gaudi2_init_qman(hdev, reg_base, queue_id_base);  in gaudi2_init_dcore_mme()
5531 	u32 queue_id_base;  in gaudi2_init_tpc_config()  local
5534 	queue_id_base = cfg_data->dcore_tpc_qid_base[dcore] + (inst * NUM_OF_PQ_PER_QMAN);  in gaudi2_init_tpc_config()
5543 	gaudi2_init_qman(hdev, mmDCORE0_TPC0_QM_BASE + offset, queue_id_base);  in gaudi2_init_tpc_config()