5949 static int gaudi2_mmu_init_common(struct hl_device *hdev, u32 mmu_base, u32 stlb_base,  in gaudi2_mmu_init_common()  argument
5977 	WREG32(mmu_base + MMU_BYPASS_OFFSET, 0);  in gaudi2_mmu_init_common()
5990 	WREG32(mmu_base + MMU_ENABLE_OFFSET, 1);  in gaudi2_mmu_init_common()
5999 	u32 mmu_base, stlb_base;  in gaudi2_pci_mmu_init()  local
6005 	mmu_base = mmPMMU_HBW_MMU_BASE;  in gaudi2_pci_mmu_init()
6024 		RMWREG32_SHIFTED(mmu_base + MMU_STATIC_MULTI_PAGE_SIZE_OFFSET,  in gaudi2_pci_mmu_init()
6035 	WREG32(mmu_base + MMU_SPI_SEI_MASK_OFFSET, GAUDI2_PMMU_SPI_SEI_ENABLE_MASK);  in gaudi2_pci_mmu_init()
6037 	rc = gaudi2_mmu_init_common(hdev, mmu_base, stlb_base, prop->pmmu.host_resident);  in gaudi2_pci_mmu_init()
6051 	u32 offset, mmu_base, stlb_base, hw_cap;  in gaudi2_dcore_hmmu_init()  local
6066 	mmu_base = mmDCORE0_HMMU0_MMU_BASE + offset;  in gaudi2_dcore_hmmu_init()
6069 	RMWREG32(mmu_base + MMU_STATIC_MULTI_PAGE_SIZE_OFFSET, 5 /* 64MB */,  in gaudi2_dcore_hmmu_init()
6087 	WREG32(mmu_base + MMU_SPI_SEI_MASK_OFFSET, GAUDI2_HMMU_SPI_SEI_ENABLE_MASK);  in gaudi2_dcore_hmmu_init()
6089 	rc = gaudi2_mmu_init_common(hdev, mmu_base, stlb_base, prop->dmmu.host_resident);  in gaudi2_dcore_hmmu_init()
8996 static void gaudi2_handle_page_error(struct hl_device *hdev, u64 mmu_base, bool is_pmmu,  in gaudi2_handle_page_error()  argument
9002 	valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID));  in gaudi2_handle_page_error()
9007 	val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE));  in gaudi2_handle_page_error()
9010 	addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_PAGE_ERROR_CAPTURE_VA));  in gaudi2_handle_page_error()
9023 	WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID), 0);  in gaudi2_handle_page_error()
9026 static void gaudi2_handle_access_error(struct hl_device *hdev, u64 mmu_base, bool is_pmmu)  in gaudi2_handle_access_error()  argument
9031 	valid = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID));  in gaudi2_handle_access_error()
9036 	val = RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE));  in gaudi2_handle_access_error()
9039 	addr |= RREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_ERROR_CAPTURE_VA));  in gaudi2_handle_access_error()
9046 	WREG32(mmu_base + MMU_OFFSET(mmDCORE0_HMMU0_MMU_ACCESS_PAGE_ERROR_VALID), 0);  in gaudi2_handle_access_error()
9050 						u64 mmu_base, bool is_pmmu, u64 *event_mask)  in gaudi2_handle_mmu_spi_sei_generic()  argument
9055 	spi_sei_cause = RREG32(mmu_base + MMU_SPI_SEI_CAUSE_OFFSET);  in gaudi2_handle_mmu_spi_sei_generic()
9063 				gaudi2_handle_page_error(hdev, mmu_base, is_pmmu, event_mask);  in gaudi2_handle_mmu_spi_sei_generic()
9065 				gaudi2_handle_access_error(hdev, mmu_base, is_pmmu);  in gaudi2_handle_mmu_spi_sei_generic()
9075 	WREG32_AND(mmu_base + MMU_SPI_SEI_CAUSE_OFFSET, ~spi_sei_cause);  in gaudi2_handle_mmu_spi_sei_generic()
9078 	WREG32(mmu_base + MMU_INTERRUPT_CLR_OFFSET, interrupt_clr);  in gaudi2_handle_mmu_spi_sei_generic()
9234 	u64 mmu_base;  in gaudi2_handle_mmu_spi_sei_err()  local
9239 		mmu_base = get_hmmu_base(event_type);  in gaudi2_handle_mmu_spi_sei_err()
9245 		mmu_base = mmPMMU_HBW_MMU_BASE;  in gaudi2_handle_mmu_spi_sei_err()
9251 	if (mmu_base == ULONG_MAX)  in gaudi2_handle_mmu_spi_sei_err()
9254 	error_count = gaudi2_handle_mmu_spi_sei_generic(hdev, event_type, mmu_base,  in gaudi2_handle_mmu_spi_sei_err()
11287 static int gaudi2_get_mmu_base(struct hl_device *hdev, u64 mmu_id, u32 *mmu_base)  in gaudi2_get_mmu_base()  argument
11291 		*mmu_base = mmDCORE0_HMMU0_MMU_BASE;  in gaudi2_get_mmu_base()
11294 		*mmu_base = mmDCORE0_HMMU1_MMU_BASE;  in gaudi2_get_mmu_base()
11297 		*mmu_base = mmDCORE0_HMMU2_MMU_BASE;  in gaudi2_get_mmu_base()
11300 		*mmu_base = mmDCORE0_HMMU3_MMU_BASE;  in gaudi2_get_mmu_base()
11303 		*mmu_base = mmDCORE1_HMMU0_MMU_BASE;  in gaudi2_get_mmu_base()
11306 		*mmu_base = mmDCORE1_HMMU1_MMU_BASE;  in gaudi2_get_mmu_base()
11309 		*mmu_base = mmDCORE1_HMMU2_MMU_BASE;  in gaudi2_get_mmu_base()
11312 		*mmu_base = mmDCORE1_HMMU3_MMU_BASE;  in gaudi2_get_mmu_base()
11315 		*mmu_base = mmDCORE2_HMMU0_MMU_BASE;  in gaudi2_get_mmu_base()
11318 		*mmu_base = mmDCORE2_HMMU1_MMU_BASE;  in gaudi2_get_mmu_base()
11321 		*mmu_base = mmDCORE2_HMMU2_MMU_BASE;  in gaudi2_get_mmu_base()
11324 		*mmu_base = mmDCORE2_HMMU3_MMU_BASE;  in gaudi2_get_mmu_base()
11327 		*mmu_base = mmDCORE3_HMMU0_MMU_BASE;  in gaudi2_get_mmu_base()
11330 		*mmu_base = mmDCORE3_HMMU1_MMU_BASE;  in gaudi2_get_mmu_base()
11333 		*mmu_base = mmDCORE3_HMMU2_MMU_BASE;  in gaudi2_get_mmu_base()
11336 		*mmu_base = mmDCORE3_HMMU3_MMU_BASE;  in gaudi2_get_mmu_base()
11339 		*mmu_base = mmPMMU_HBW_MMU_BASE;  in gaudi2_get_mmu_base()
11352 	u32 mmu_base;  in gaudi2_ack_mmu_error()  local
11357 	if (gaudi2_get_mmu_base(hdev, mmu_id, &mmu_base))  in gaudi2_ack_mmu_error()
11360 	gaudi2_handle_page_error(hdev, mmu_base, is_pmmu, NULL);  in gaudi2_ack_mmu_error()
11361 	gaudi2_handle_access_error(hdev, mmu_base, is_pmmu);  in gaudi2_ack_mmu_error()