17 static int aie2_pm_set_clk_gating(struct amdxdna_dev_hdl *ndev, u32 val)  in aie2_pm_set_clk_gating()  argument
21 	ret = aie2_runtime_cfg(ndev, AIE2_RT_CFG_CLK_GATING, &val);  in aie2_pm_set_clk_gating()
25 	ndev->clk_gating = val;  in aie2_pm_set_clk_gating()
29 int aie2_pm_init(struct amdxdna_dev_hdl *ndev)  in aie2_pm_init()  argument
33 	if (ndev->dev_status != AIE2_DEV_UNINIT) {  in aie2_pm_init()
35 		ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->dpm_level);  in aie2_pm_init()
39 		ret = aie2_pm_set_clk_gating(ndev, ndev->clk_gating);  in aie2_pm_init()
46 	while (ndev->priv->dpm_clk_tbl[ndev->max_dpm_level].hclk)  in aie2_pm_init()
47 		ndev->max_dpm_level++;  in aie2_pm_init()
48 	ndev->max_dpm_level--;  in aie2_pm_init()
50 	ret = ndev->priv->hw_ops.set_dpm(ndev, ndev->max_dpm_level);  in aie2_pm_init()
54 	ret = aie2_pm_set_clk_gating(ndev, AIE2_CLK_GATING_ENABLE);  in aie2_pm_init()
58 	ndev->pw_mode = POWER_MODE_DEFAULT;  in aie2_pm_init()
59 	ndev->dft_dpm_level = ndev->max_dpm_level;  in aie2_pm_init()
64 int aie2_pm_set_mode(struct amdxdna_dev_hdl *ndev, enum amdxdna_power_mode_type target)  in aie2_pm_set_mode()  argument
66 	struct amdxdna_dev *xdna = ndev->xdna;  in aie2_pm_set_mode()
72 	if (ndev->pw_mode == target)  in aie2_pm_set_mode()
77 		if (ndev->hwctx_num) {  in aie2_pm_set_mode()
83 		dpm_level = ndev->max_dpm_level;  in aie2_pm_set_mode()
87 		dpm_level = ndev->max_dpm_level;  in aie2_pm_set_mode()
91 		dpm_level = ndev->dft_dpm_level;  in aie2_pm_set_mode()
97 	ret = ndev->priv->hw_ops.set_dpm(ndev, dpm_level);  in aie2_pm_set_mode()
101 	ret = aie2_pm_set_clk_gating(ndev, clk_gating);  in aie2_pm_set_mode()
105 	ndev->pw_mode = target;  in aie2_pm_set_mode()