Lines Matching +full:64 +full:m
38 vld1q_u8(state + 64) in aegis128_load_state_neon()
48 vst1q_u8(state + 64, st.v[4]); in aegis128_save_state_neon()
108 uint8x16_t m) in aegis128_update_neon() argument
110 m ^= aegis_aes_round(st.v[4]); in aegis128_update_neon()
115 st.v[0] ^= m; in aegis128_update_neon()
128 asm("ld1 {v16.16b-v19.16b}, [%0], #64 \n\t" in preload_sbox()
129 "ld1 {v20.16b-v23.16b}, [%0], #64 \n\t" in preload_sbox()
130 "ld1 {v24.16b-v27.16b}, [%0], #64 \n\t" in preload_sbox()
179 * implement the underlying instructions. AArch32 only provides 64-bit
216 static const uint8_t permute[] __aligned(64) = {
249 uint8x16_t m; in crypto_aegis128_encrypt_chunk_neon() local
254 m = vqtbl1q_u8(vld1q_u8(in + size - AEGIS_BLOCK_SIZE), in crypto_aegis128_encrypt_chunk_neon()
257 st = aegis128_update_neon(st, m); in crypto_aegis128_encrypt_chunk_neon()
260 vqtbl1q_u8(m ^ s, vld1q_u8(permute + size))); in crypto_aegis128_encrypt_chunk_neon()
295 uint8x16_t m; in crypto_aegis128_decrypt_chunk_neon() local
300 m = s ^ vqtbx1q_u8(s, vld1q_u8(in + size - AEGIS_BLOCK_SIZE), in crypto_aegis128_decrypt_chunk_neon()
303 st = aegis128_update_neon(st, m); in crypto_aegis128_decrypt_chunk_neon()
306 vqtbl1q_u8(m, vld1q_u8(permute + size))); in crypto_aegis128_decrypt_chunk_neon()